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Searched refs:pin_mask (Results 1 – 11 of 11) sorted by relevance

/drivers/gpio/
Dgpio-mxs.c87 u32 pin_mask = 1 << d->hwirq; in mxs_gpio_set_irq_type() local
98 port->both_edges &= ~pin_mask; in mxs_gpio_set_irq_type()
106 port->both_edges |= pin_mask; in mxs_gpio_set_irq_type()
127 writel(pin_mask, pin_addr + MXS_SET); in mxs_gpio_set_irq_type()
128 writel(pin_mask, port->base + PINCTRL_IRQEN(port) + MXS_SET); in mxs_gpio_set_irq_type()
130 writel(pin_mask, pin_addr + MXS_CLR); in mxs_gpio_set_irq_type()
131 writel(pin_mask, port->base + PINCTRL_PIN2IRQ(port) + MXS_SET); in mxs_gpio_set_irq_type()
137 writel(pin_mask, pin_addr + MXS_SET); in mxs_gpio_set_irq_type()
139 writel(pin_mask, pin_addr + MXS_CLR); in mxs_gpio_set_irq_type()
141 writel(pin_mask, in mxs_gpio_set_irq_type()
Dgpio-tegra.c201 u32 pin_mask = BIT(GPIO_BIT(offset)); in tegra_gpio_get_direction() local
205 if (!(cnf & pin_mask)) in tegra_gpio_get_direction()
210 return (oe & pin_mask) ? GPIOF_DIR_OUT : GPIOF_DIR_IN; in tegra_gpio_get_direction()
/drivers/soc/fsl/qe/
Dqe_io.c131 u32 pin_mask, tmp_val; in par_io_data_set() local
138 pin_mask = (u32) (1 << (QE_PIO_PINS - 1 - pin)); in par_io_data_set()
143 out_be32(&par_io[port].cpdata, ~pin_mask & tmp_val); in par_io_data_set()
145 out_be32(&par_io[port].cpdata, pin_mask | tmp_val); in par_io_data_set()
Dgpio.c61 u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio); in qe_gpio_get() local
63 return !!(in_be32(&regs->cpdata) & pin_mask); in qe_gpio_get()
72 u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio); in qe_gpio_set() local
77 qe_gc->cpdata |= pin_mask; in qe_gpio_set()
79 qe_gc->cpdata &= ~pin_mask; in qe_gpio_set()
/drivers/gpu/drm/nouveau/dispnv04/
Dtvnv17.c130 get_tv_detect_quirks(struct drm_device *dev, uint32_t *pin_mask) in get_tv_detect_quirks() argument
136 *pin_mask = device->quirk->tv_pin_mask; in get_tv_detect_quirks()
151 bool reliable = get_tv_detect_quirks(dev, &tv_enc->pin_mask); in nv17_tv_detect()
159 tv_enc->pin_mask = in nv17_tv_detect()
162 tv_enc->pin_mask = in nv17_tv_detect()
166 switch (tv_enc->pin_mask) { in nv17_tv_detect()
807 tv_enc->pin_mask = 0; in nv17_tv_create()
Dtvnv17.h83 uint32_t pin_mask; member
Dtvmodesnv17.c488 if (tv_enc->pin_mask & 0x4) in nv17_tv_update_properties()
490 else if (tv_enc->pin_mask & 0x2) in nv17_tv_update_properties()
/drivers/gpu/drm/i915/
Di915_irq.c1487 static void intel_get_hpd_pins(u32 *pin_mask, u32 *long_mask, in intel_get_hpd_pins() argument
1499 *pin_mask |= BIT(i); in intel_get_hpd_pins()
1510 hotplug_trigger, dig_hotplug_reg, *pin_mask); in intel_get_hpd_pins()
1828 u32 pin_mask = 0, long_mask = 0; in i9xx_hpd_irq_handler() local
1835 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger, in i9xx_hpd_irq_handler()
1839 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); in i9xx_hpd_irq_handler()
1848 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger, in i9xx_hpd_irq_handler()
1851 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); in i9xx_hpd_irq_handler()
2029 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0; in ibx_hpd_irq_handler() local
2050 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger, in ibx_hpd_irq_handler()
[all …]
Dintel_hotplug.c404 u32 pin_mask, u32 long_mask) in intel_hpd_irq_handler() argument
412 if (!pin_mask) in intel_hpd_irq_handler()
417 if (!(BIT(i) & pin_mask)) in intel_hpd_irq_handler()
Di915_drv.h3205 u32 pin_mask, u32 long_mask);
/drivers/pinctrl/
Dpinctrl-st.c1094 u32 pin_mask = pc->rt_pin_mask; in st_pctl_dt_setup_retime_dedicated() local
1097 if (BIT(j) & pin_mask) { in st_pctl_dt_setup_retime_dedicated()