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Searched refs:reg_addr (Results 1 – 25 of 158) sorted by relevance

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/drivers/staging/rtlwifi/phydm/
Dphydm_interface.c37 u8 odm_read_1byte(struct phy_dm_struct *dm, u32 reg_addr) in odm_read_1byte() argument
41 return rtl_read_byte(rtlpriv, reg_addr); in odm_read_1byte()
44 u16 odm_read_2byte(struct phy_dm_struct *dm, u32 reg_addr) in odm_read_2byte() argument
48 return rtl_read_word(rtlpriv, reg_addr); in odm_read_2byte()
51 u32 odm_read_4byte(struct phy_dm_struct *dm, u32 reg_addr) in odm_read_4byte() argument
55 return rtl_read_dword(rtlpriv, reg_addr); in odm_read_4byte()
58 void odm_write_1byte(struct phy_dm_struct *dm, u32 reg_addr, u8 data) in odm_write_1byte() argument
62 rtl_write_byte(rtlpriv, reg_addr, data); in odm_write_1byte()
65 void odm_write_2byte(struct phy_dm_struct *dm, u32 reg_addr, u16 data) in odm_write_2byte() argument
69 rtl_write_word(rtlpriv, reg_addr, data); in odm_write_2byte()
[all …]
Dphydm_interface.h111 u8 odm_read_1byte(struct phy_dm_struct *dm, u32 reg_addr);
113 u16 odm_read_2byte(struct phy_dm_struct *dm, u32 reg_addr);
115 u32 odm_read_4byte(struct phy_dm_struct *dm, u32 reg_addr);
117 void odm_write_1byte(struct phy_dm_struct *dm, u32 reg_addr, u8 data);
119 void odm_write_2byte(struct phy_dm_struct *dm, u32 reg_addr, u16 data);
121 void odm_write_4byte(struct phy_dm_struct *dm, u32 reg_addr, u32 data);
123 void odm_set_mac_reg(struct phy_dm_struct *dm, u32 reg_addr, u32 bit_mask,
126 u32 odm_get_mac_reg(struct phy_dm_struct *dm, u32 reg_addr, u32 bit_mask);
128 void odm_set_bb_reg(struct phy_dm_struct *dm, u32 reg_addr, u32 bit_mask,
131 u32 odm_get_bb_reg(struct phy_dm_struct *dm, u32 reg_addr, u32 bit_mask);
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/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/
Disys_irq_private.h74 unsigned int reg_addr; in isys_irqc_reg_store() local
79 reg_addr = ISYS_IRQ_BASE[isys_irqc_id] + (reg_idx * sizeof(hrt_data)); in isys_irqc_reg_store()
81 "isys irq store at addr(0x%x) val(%u)\n", reg_addr, (unsigned int)value); in isys_irqc_reg_store()
83 ia_css_device_store_uint32(reg_addr, value); in isys_irqc_reg_store()
90 unsigned int reg_addr; in isys_irqc_reg_load() local
96 reg_addr = ISYS_IRQ_BASE[isys_irqc_id] + (reg_idx * sizeof(hrt_data)); in isys_irqc_reg_load()
97 value = ia_css_device_load_uint32(reg_addr); in isys_irqc_reg_load()
99 "isys irq load from addr(0x%x) val(%u)\n", reg_addr, (unsigned int)value); in isys_irqc_reg_load()
/drivers/iio/common/st_sensors/
Dst_sensors_spi.c30 struct device *dev, u8 reg_addr, int len, u8 *data, bool multiread_bit) in st_sensors_spi_read() argument
49 tb->tx_buf[0] = reg_addr | ST_SENSORS_SPI_MULTIREAD; in st_sensors_spi_read()
51 tb->tx_buf[0] = reg_addr | ST_SENSORS_SPI_READ; in st_sensors_spi_read()
67 struct device *dev, u8 reg_addr, u8 *res_byte) in st_sensors_spi_read_byte() argument
69 return st_sensors_spi_read(tb, dev, reg_addr, 1, res_byte, false); in st_sensors_spi_read_byte()
74 u8 reg_addr, int len, u8 *data, bool multiread_bit) in st_sensors_spi_read_multiple_byte() argument
76 return st_sensors_spi_read(tb, dev, reg_addr, len, data, multiread_bit); in st_sensors_spi_read_multiple_byte()
80 struct device *dev, u8 reg_addr, u8 data) in st_sensors_spi_write_byte() argument
91 tb->tx_buf[0] = reg_addr; in st_sensors_spi_write_byte()
Dst_sensors_i2c.c31 struct device *dev, u8 reg_addr, u8 *res_byte) in st_sensors_i2c_read_byte() argument
35 err = i2c_smbus_read_byte_data(to_i2c_client(dev), reg_addr); in st_sensors_i2c_read_byte()
47 u8 reg_addr, int len, u8 *data, bool multiread_bit) in st_sensors_i2c_read_multiple_byte() argument
50 reg_addr |= ST_SENSORS_I2C_MULTIREAD; in st_sensors_i2c_read_multiple_byte()
53 reg_addr, len, data); in st_sensors_i2c_read_multiple_byte()
57 struct device *dev, u8 reg_addr, u8 data) in st_sensors_i2c_write_byte() argument
59 return i2c_smbus_write_byte_data(to_i2c_client(dev), reg_addr, data); in st_sensors_i2c_write_byte()
/drivers/input/touchscreen/
Dedt-ft5x06.c112 struct edt_reg_addr reg_addr; member
557 struct edt_reg_addr *reg_addr = &tsdata->reg_addr; in edt_ft5x06_work_mode() local
590 edt_ft5x06_register_write(tsdata, reg_addr->reg_threshold, in edt_ft5x06_work_mode()
592 edt_ft5x06_register_write(tsdata, reg_addr->reg_gain, in edt_ft5x06_work_mode()
594 edt_ft5x06_register_write(tsdata, reg_addr->reg_offset, in edt_ft5x06_work_mode()
596 if (reg_addr->reg_report_rate != NO_REGISTER) in edt_ft5x06_work_mode()
597 edt_ft5x06_register_write(tsdata, reg_addr->reg_report_rate, in edt_ft5x06_work_mode()
821 struct edt_reg_addr *reg_addr = &tsdata->reg_addr; in edt_ft5x06_ts_get_defaults() local
827 edt_ft5x06_register_write(tsdata, reg_addr->reg_threshold, val); in edt_ft5x06_ts_get_defaults()
833 edt_ft5x06_register_write(tsdata, reg_addr->reg_gain, val); in edt_ft5x06_ts_get_defaults()
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/drivers/infiniband/hw/qib/
Dqib_diag.c342 const u64 __iomem *reg_addr; in qib_read_umem64() local
347 reg_addr = (const u64 __iomem *)qib_remap_ioaddr32(dd, regoffs, &limit); in qib_read_umem64()
348 if (reg_addr == NULL || limit == 0 || !(dd->flags & QIB_PRESENT)) { in qib_read_umem64()
354 reg_end = reg_addr + (count / sizeof(u64)); in qib_read_umem64()
357 while (reg_addr < reg_end) { in qib_read_umem64()
358 u64 data = readq(reg_addr); in qib_read_umem64()
364 reg_addr++; in qib_read_umem64()
386 u64 __iomem *reg_addr; in qib_write_umem64() local
391 reg_addr = (u64 __iomem *)qib_remap_ioaddr32(dd, regoffs, &limit); in qib_write_umem64()
392 if (reg_addr == NULL || limit == 0 || !(dd->flags & QIB_PRESENT)) { in qib_write_umem64()
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/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/
Dinput_formatter_private.h26 const hrt_address reg_addr, in input_formatter_reg_store() argument
31 assert((reg_addr % sizeof(hrt_data)) == 0); in input_formatter_reg_store()
32 ia_css_device_store_uint32(INPUT_FORMATTER_BASE[ID] + reg_addr, value); in input_formatter_reg_store()
38 const unsigned int reg_addr) in input_formatter_reg_load() argument
42 assert((reg_addr % sizeof(hrt_data)) == 0); in input_formatter_reg_load()
43 return ia_css_device_load_uint32(INPUT_FORMATTER_BASE[ID] + reg_addr); in input_formatter_reg_load()
Dgp_device_private.h26 const unsigned int reg_addr, in gp_device_reg_store() argument
31 assert((reg_addr % sizeof(hrt_data)) == 0); in gp_device_reg_store()
32 ia_css_device_store_uint32(GP_DEVICE_BASE[ID] + reg_addr, value); in gp_device_reg_store()
38 const hrt_address reg_addr) in gp_device_reg_load() argument
42 assert((reg_addr % sizeof(hrt_data)) == 0); in gp_device_reg_load()
43 return ia_css_device_load_uint32(GP_DEVICE_BASE[ID] + reg_addr); in gp_device_reg_load()
/drivers/net/ethernet/hisilicon/hns/
Dhns_dsaf_misc.c245 u32 reg_addr; in hns_dsaf_xge_srst_by_port() local
254 reg_addr = DSAF_SUB_SC_XGE_RESET_REQ_REG; in hns_dsaf_xge_srst_by_port()
256 reg_addr = DSAF_SUB_SC_XGE_RESET_DREQ_REG; in hns_dsaf_xge_srst_by_port()
258 dsaf_write_sub(dsaf_dev, reg_addr, reg_val); in hns_dsaf_xge_srst_by_port()
280 u32 reg_addr; in hns_dsaf_srst_chns() local
283 reg_addr = DSAF_SUB_SC_DSAF_RESET_REQ_REG; in hns_dsaf_srst_chns()
285 reg_addr = DSAF_SUB_SC_DSAF_RESET_DREQ_REG; in hns_dsaf_srst_chns()
287 dsaf_write_sub(dsaf_dev, reg_addr, msk); in hns_dsaf_srst_chns()
393 u32 reg_addr; in hns_ppe_srst_by_port() local
398 reg_addr = DSAF_SUB_SC_PPE_RESET_REQ_REG; in hns_ppe_srst_by_port()
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/drivers/net/wireless/realtek/rtlwifi/btcoexist/
Dhalbtcoutsrc.h420 typedef u8 (*bfp_btc_r1)(void *btc_context, u32 reg_addr);
422 typedef u16 (*bfp_btc_r2)(void *btc_context, u32 reg_addr);
424 typedef u32 (*bfp_btc_r4)(void *btc_context, u32 reg_addr);
426 typedef void (*bfp_btc_w1)(void *btc_context, u32 reg_addr, u32 data);
428 typedef void (*bfp_btc_w1_bit_mak)(void *btc_context, u32 reg_addr,
431 typedef void (*bfp_btc_w2)(void *btc_context, u32 reg_addr, u16 data);
433 typedef void (*bfp_btc_w4)(void *btc_context, u32 reg_addr, u32 data);
435 typedef void (*bfp_btc_local_reg_w1)(void *btc_context, u32 reg_addr, u8 data);
436 typedef void (*bfp_btc_wr_1byte_bit_mask)(void *btc_context, u32 reg_addr,
439 typedef void (*bfp_btc_set_bb_reg)(void *btc_context, u32 reg_addr,
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Dhalbtcoutsrc.c644 static u8 halbtc_read_1byte(void *bt_context, u32 reg_addr) in halbtc_read_1byte() argument
649 return rtl_read_byte(rtlpriv, reg_addr); in halbtc_read_1byte()
652 static u16 halbtc_read_2byte(void *bt_context, u32 reg_addr) in halbtc_read_2byte() argument
657 return rtl_read_word(rtlpriv, reg_addr); in halbtc_read_2byte()
660 static u32 halbtc_read_4byte(void *bt_context, u32 reg_addr) in halbtc_read_4byte() argument
665 return rtl_read_dword(rtlpriv, reg_addr); in halbtc_read_4byte()
668 static void halbtc_write_1byte(void *bt_context, u32 reg_addr, u32 data) in halbtc_write_1byte() argument
673 rtl_write_byte(rtlpriv, reg_addr, data); in halbtc_write_1byte()
676 static void halbtc_bitmask_write_1byte(void *bt_context, u32 reg_addr, in halbtc_bitmask_write_1byte() argument
685 original_value = rtl_read_byte(rtlpriv, reg_addr); in halbtc_bitmask_write_1byte()
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/drivers/net/ethernet/broadcom/bnx2x/
Dbnx2x_dump.h46 struct reg_addr { struct
67 static const struct reg_addr page_read_regs_e2[] = { argument
76 static const struct reg_addr page_read_regs_e3[] = {
80 static const struct reg_addr reg_addrs[] = {
1901 static const struct reg_addr idle_reg_addrs[] = {
Dbnx2x_init.h215 u32 reg_addr, reg_bit_map, vnic; in bnx2x_map_q_cos() local
236 reg_addr = BNX2X_VOQ_Q_REG_ADDR(curr_cos, pf_q_num); in bnx2x_map_q_cos()
237 reg_bit_map = REG_RD(bp, reg_addr); in bnx2x_map_q_cos()
238 REG_WR(bp, reg_addr, reg_bit_map & (~q_bit_map)); in bnx2x_map_q_cos()
241 reg_addr = BNX2X_VOQ_Q_REG_ADDR(new_cos, pf_q_num); in bnx2x_map_q_cos()
242 reg_bit_map = REG_RD(bp, reg_addr); in bnx2x_map_q_cos()
243 REG_WR(bp, reg_addr, reg_bit_map | q_bit_map); in bnx2x_map_q_cos()
249 reg_addr = BNX2X_Q_CMDQ_REG_ADDR(pf_q_num); in bnx2x_map_q_cos()
250 reg_bit_map = REG_RD(bp, reg_addr); in bnx2x_map_q_cos()
255 REG_WR(bp, reg_addr, reg_bit_map); in bnx2x_map_q_cos()
/drivers/media/pci/cx25821/
Dcx25821-i2c.c92 cx_write(bus->reg_addr, msg->addr << 25); in i2c_sendbytes()
116 cx_write(bus->reg_addr, addr); in i2c_sendbytes()
142 cx_write(bus->reg_addr, addr); in i2c_sendbytes()
183 cx_write(bus->reg_addr, msg->addr << 25); in i2c_readbytes()
208 cx_write(bus->reg_addr, msg->addr << 25); in i2c_readbytes()
354 int cx25821_i2c_read(struct cx25821_i2c *bus, u16 reg_addr, int *value) in cx25821_i2c_read() argument
375 addr[0] = (reg_addr >> 8); in cx25821_i2c_read()
376 addr[1] = (reg_addr & 0xff); in cx25821_i2c_read()
388 int cx25821_i2c_write(struct cx25821_i2c *bus, u16 reg_addr, int value) in cx25821_i2c_write() argument
403 buf[0] = reg_addr >> 8; in cx25821_i2c_write()
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/drivers/pinctrl/mediatek/
Dpinctrl-mtk-common.c79 unsigned int reg_addr; in mtk_pmx_gpio_set_direction() local
83 reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset; in mtk_pmx_gpio_set_direction()
87 pctl->devdata->spec_dir_set(&reg_addr, offset); in mtk_pmx_gpio_set_direction()
91 reg_addr = CLR_ADDR(reg_addr, pctl); in mtk_pmx_gpio_set_direction()
93 reg_addr = SET_ADDR(reg_addr, pctl); in mtk_pmx_gpio_set_direction()
95 regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit); in mtk_pmx_gpio_set_direction()
101 unsigned int reg_addr; in mtk_gpio_set() local
105 reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dout_offset; in mtk_gpio_set()
109 reg_addr = SET_ADDR(reg_addr, pctl); in mtk_gpio_set()
111 reg_addr = CLR_ADDR(reg_addr, pctl); in mtk_gpio_set()
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/drivers/net/ethernet/chelsio/cxgb4vf/
Dadapter.h426 static inline u32 t4_read_reg(struct adapter *adapter, u32 reg_addr) in t4_read_reg() argument
428 return readl(adapter->regs + reg_addr); in t4_read_reg()
439 static inline void t4_write_reg(struct adapter *adapter, u32 reg_addr, u32 val) in t4_write_reg() argument
441 writel(val, adapter->regs + reg_addr); in t4_write_reg()
464 static inline u64 t4_read_reg64(struct adapter *adapter, u32 reg_addr) in t4_read_reg64() argument
466 return readq(adapter->regs + reg_addr); in t4_read_reg64()
477 static inline void t4_write_reg64(struct adapter *adapter, u32 reg_addr, in t4_write_reg64() argument
480 writeq(val, adapter->regs + reg_addr); in t4_write_reg64()
/drivers/staging/rtlwifi/btcoexist/
Dhalbtcoutsrc.h448 typedef u8 (*bfp_btc_r1)(void *btc_context, u32 reg_addr);
450 typedef u16 (*bfp_btc_r2)(void *btc_context, u32 reg_addr);
452 typedef u32 (*bfp_btc_r4)(void *btc_context, u32 reg_addr);
454 typedef void (*bfp_btc_w1)(void *btc_context, u32 reg_addr, u32 data);
456 typedef void (*bfp_btc_w1_bit_mak)(void *btc_context, u32 reg_addr,
459 typedef void (*bfp_btc_w2)(void *btc_context, u32 reg_addr, u16 data);
461 typedef void (*bfp_btc_w4)(void *btc_context, u32 reg_addr, u32 data);
463 typedef void (*bfp_btc_local_reg_w1)(void *btc_context, u32 reg_addr, u8 data);
464 typedef void (*bfp_btc_wr_1byte_bit_mask)(void *btc_context, u32 reg_addr,
467 typedef void (*bfp_btc_set_bb_reg)(void *btc_context, u32 reg_addr,
[all …]
Dhalbtcoutsrc.c881 static u8 halbtc_read_1byte(void *bt_context, u32 reg_addr) in halbtc_read_1byte() argument
886 return rtl_read_byte(rtlpriv, reg_addr); in halbtc_read_1byte()
889 static u16 halbtc_read_2byte(void *bt_context, u32 reg_addr) in halbtc_read_2byte() argument
894 return rtl_read_word(rtlpriv, reg_addr); in halbtc_read_2byte()
897 static u32 halbtc_read_4byte(void *bt_context, u32 reg_addr) in halbtc_read_4byte() argument
902 return rtl_read_dword(rtlpriv, reg_addr); in halbtc_read_4byte()
905 static void halbtc_write_1byte(void *bt_context, u32 reg_addr, u32 data) in halbtc_write_1byte() argument
910 rtl_write_byte(rtlpriv, reg_addr, data); in halbtc_write_1byte()
913 static void halbtc_bitmask_write_1byte(void *bt_context, u32 reg_addr, in halbtc_bitmask_write_1byte() argument
922 original_value = rtl_read_byte(rtlpriv, reg_addr); in halbtc_bitmask_write_1byte()
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/drivers/staging/rtl8192u/
Dr819xU_phy.h62 void rtl8192_setBBreg(struct net_device *dev, u32 reg_addr,
64 u32 rtl8192_QueryBBReg(struct net_device *dev, u32 reg_addr, u32 bitmask);
66 u32 reg_addr, u32 bitmask, u32 data);
68 u32 reg_addr, u32 bitmask);
/drivers/crypto/qat/qat_common/
Dqat_hal.c269 unsigned short reg_addr; in qat_hal_get_reg_addr() local
274 reg_addr = 0x80 | (reg_num & 0x7f); in qat_hal_get_reg_addr()
278 reg_addr = reg_num & 0x1f; in qat_hal_get_reg_addr()
283 reg_addr = 0x180 | (reg_num & 0x1f); in qat_hal_get_reg_addr()
286 reg_addr = 0x140 | ((reg_num & 0x3) << 1); in qat_hal_get_reg_addr()
291 reg_addr = 0x1c0 | (reg_num & 0x1f); in qat_hal_get_reg_addr()
294 reg_addr = 0x100 | ((reg_num & 0x3) << 1); in qat_hal_get_reg_addr()
297 reg_addr = 0x280 | (reg_num & 0x1f); in qat_hal_get_reg_addr()
300 reg_addr = 0x200; in qat_hal_get_reg_addr()
303 reg_addr = 0x220; in qat_hal_get_reg_addr()
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/drivers/net/ethernet/chelsio/cxgb3/
Dadapter.h270 static inline u32 t3_read_reg(struct adapter *adapter, u32 reg_addr) in t3_read_reg() argument
272 u32 val = readl(adapter->regs + reg_addr); in t3_read_reg()
274 CH_DBG(adapter, MMIO, "read register 0x%x value 0x%x\n", reg_addr, val); in t3_read_reg()
278 static inline void t3_write_reg(struct adapter *adapter, u32 reg_addr, u32 val) in t3_write_reg() argument
280 CH_DBG(adapter, MMIO, "setting register 0x%x to 0x%x\n", reg_addr, val); in t3_write_reg()
281 writel(val, adapter->regs + reg_addr); in t3_write_reg()
/drivers/staging/most/hdm-usb/
Dhdm_usb.c75 u16 reg_addr; member
955 const char *name, u16 *reg_addr) in get_stat_reg_addr() argument
961 *reg_addr = regs[i].reg; in get_stat_reg_addr()
968 #define get_static_reg_addr(regs, name, reg_addr) \ argument
969 get_stat_reg_addr(regs, ARRAY_SIZE(regs), name, reg_addr)
976 u16 reg_addr; in show_value() local
980 return snprintf(buf, PAGE_SIZE, "%04x\n", dci_obj->reg_addr); in show_value()
983 reg_addr = dci_obj->reg_addr; in show_value()
984 else if (get_static_reg_addr(ro_regs, name, &reg_addr) && in show_value()
985 get_static_reg_addr(rw_regs, name, &reg_addr)) in show_value()
[all …]
/drivers/media/platform/ti-vpe/
Dvpdma.c583 void vpdma_set_max_size(struct vpdma_data *vpdma, int reg_addr, in vpdma_set_max_size() argument
586 if (reg_addr != VPDMA_MAX_SIZE1 && reg_addr != VPDMA_MAX_SIZE2 && in vpdma_set_max_size()
587 reg_addr != VPDMA_MAX_SIZE3) in vpdma_set_max_size()
588 reg_addr = VPDMA_MAX_SIZE1; in vpdma_set_max_size()
590 write_field_reg(vpdma, reg_addr, width - 1, in vpdma_set_max_size()
593 write_field_reg(vpdma, reg_addr, height - 1, in vpdma_set_max_size()
981 u32 reg_addr = VPDMA_INT_LIST0_MASK + VPDMA_INTX_OFFSET * irq_num; in vpdma_enable_list_complete_irq() local
984 val = read_reg(vpdma, reg_addr); in vpdma_enable_list_complete_irq()
989 write_reg(vpdma, reg_addr, val); in vpdma_enable_list_complete_irq()
996 u32 reg_addr = VPDMA_INT_LIST0_STAT + VPDMA_INTX_OFFSET * irq_num; in vpdma_get_list_stat() local
[all …]
/drivers/net/ethernet/cavium/thunder/
Dnic_main.c827 u64 reg_addr; in nic_reset_stat_counters() local
831 reg_addr = NIC_PF_VNIC_0_127_RX_STAT_0_13 | in nic_reset_stat_counters()
834 nic_reg_write(nic, reg_addr, 0); in nic_reset_stat_counters()
840 reg_addr = NIC_PF_VNIC_0_127_TX_STAT_0_4 | in nic_reset_stat_counters()
843 nic_reg_write(nic, reg_addr, 0); in nic_reset_stat_counters()
850 reg_addr = (vf << NIC_QS_ID_SHIFT) | in nic_reset_stat_counters()
853 reg_addr |= NIC_PF_QSET_0_127_RQ_0_7_STAT_0_1; in nic_reset_stat_counters()
854 nic_reg_write(nic, reg_addr, 0); in nic_reset_stat_counters()
857 reg_addr |= NIC_PF_QSET_0_127_SQ_0_7_STAT_0_1; in nic_reset_stat_counters()
858 nic_reg_write(nic, reg_addr, 0); in nic_reset_stat_counters()
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