Home
last modified time | relevance | path

Searched refs:reg_data (Results 1 – 25 of 73) sorted by relevance

123

/drivers/power/supply/
Dmax14577_charger.c61 u8 reg_data; in max14577_get_charger_state() local
74 ret = max14577_read_reg(rmap, MAX14577_CHG_REG_CHG_CTRL2, &reg_data); in max14577_get_charger_state()
78 if ((reg_data & CHGCTRL2_MBCHOSTEN_MASK) == 0) { in max14577_get_charger_state()
83 ret = max14577_read_reg(rmap, MAX14577_CHG_REG_STATUS3, &reg_data); in max14577_get_charger_state()
87 if (reg_data & STATUS3_CGMBC_MASK) { in max14577_get_charger_state()
89 if (reg_data & STATUS3_EOC_MASK) in max14577_get_charger_state()
134 u8 reg_data; in max14577_get_online() local
138 ret = max14577_read_reg(rmap, MAX14577_MUIC_REG_STATUS2, &reg_data); in max14577_get_online()
142 reg_data = ((reg_data & STATUS2_CHGTYP_MASK) >> STATUS2_CHGTYP_SHIFT); in max14577_get_online()
143 chg_type = maxim_get_charger_type(chg->max14577->dev_type, reg_data); in max14577_get_online()
[all …]
/drivers/clk/rockchip/
Dclk-cpu.c66 const struct rockchip_cpuclk_reg_data *reg_data; member
93 const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data; in rockchip_cpuclk_recalc_rate() local
94 u32 clksel0 = readl_relaxed(cpuclk->reg_base + reg_data->core_reg); in rockchip_cpuclk_recalc_rate()
96 clksel0 >>= reg_data->div_core_shift; in rockchip_cpuclk_recalc_rate()
97 clksel0 &= reg_data->div_core_mask; in rockchip_cpuclk_recalc_rate()
126 const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data; in rockchip_cpuclk_pre_rate_change() local
152 if (alt_div > reg_data->div_core_mask) { in rockchip_cpuclk_pre_rate_change()
154 __func__, alt_div, reg_data->div_core_mask); in rockchip_cpuclk_pre_rate_change()
155 alt_div = reg_data->div_core_mask; in rockchip_cpuclk_pre_rate_change()
168 writel(HIWORD_UPDATE(alt_div, reg_data->div_core_mask, in rockchip_cpuclk_pre_rate_change()
[all …]
/drivers/net/ethernet/intel/e1000e/
D80003es2lan.c744 u32 reg_data; in e1000_init_hw_80003es2lan() local
782 reg_data = er32(TXDCTL(0)); in e1000_init_hw_80003es2lan()
783 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) | in e1000_init_hw_80003es2lan()
785 ew32(TXDCTL(0), reg_data); in e1000_init_hw_80003es2lan()
788 reg_data = er32(TXDCTL(1)); in e1000_init_hw_80003es2lan()
789 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) | in e1000_init_hw_80003es2lan()
791 ew32(TXDCTL(1), reg_data); in e1000_init_hw_80003es2lan()
794 reg_data = er32(TCTL); in e1000_init_hw_80003es2lan()
795 reg_data |= E1000_TCTL_RTLC; in e1000_init_hw_80003es2lan()
796 ew32(TCTL, reg_data); in e1000_init_hw_80003es2lan()
[all …]
D82571.c1085 u32 reg_data; in e1000_init_hw_82571() local
1119 reg_data = er32(TXDCTL(0)); in e1000_init_hw_82571()
1120 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) | in e1000_init_hw_82571()
1122 ew32(TXDCTL(0), reg_data); in e1000_init_hw_82571()
1131 reg_data = er32(GCR); in e1000_init_hw_82571()
1132 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; in e1000_init_hw_82571()
1133 ew32(GCR, reg_data); in e1000_init_hw_82571()
1136 reg_data = er32(TXDCTL(1)); in e1000_init_hw_82571()
1137 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) | in e1000_init_hw_82571()
1140 ew32(TXDCTL(1), reg_data); in e1000_init_hw_82571()
/drivers/soc/qcom/
Dspm.c74 const struct spm_reg_data *reg_data; member
126 if (drv->reg_data->reg_offset[reg]) in spm_register_write()
128 drv->reg_data->reg_offset[reg]); in spm_register_write()
137 if (!drv->reg_data->reg_offset[reg]) in spm_register_write_sync()
142 drv->reg_data->reg_offset[reg]); in spm_register_write_sync()
144 drv->reg_data->reg_offset[reg]); in spm_register_write_sync()
154 return readl_relaxed(drv->reg_base + drv->reg_data->reg_offset[reg]); in spm_register_read()
163 start_index = drv->reg_data->start_index[mode]; in spm_set_low_power_mode()
346 drv->reg_data = match_id->data; in spm_dev_probe()
349 addr = drv->reg_base + drv->reg_data->reg_offset[SPM_REG_SEQ_ENTRY]; in spm_dev_probe()
[all …]
/drivers/regulator/
Dmax14577-regulator.c29 u8 reg_data; in max14577_reg_is_enabled() local
33 max14577_read_reg(rmap, MAX14577_CHG_REG_CHG_CTRL2, &reg_data); in max14577_reg_is_enabled()
34 if ((reg_data & CHGCTRL2_MBCHOSTEN_MASK) == 0) in max14577_reg_is_enabled()
36 max14577_read_reg(rmap, MAX14577_CHG_REG_STATUS3, &reg_data); in max14577_reg_is_enabled()
37 if ((reg_data & STATUS3_CGMBC_MASK) == 0) in max14577_reg_is_enabled()
48 u8 reg_data; in max14577_reg_get_current_limit() local
57 max14577_read_reg(rmap, MAX14577_CHG_REG_CHG_CTRL4, &reg_data); in max14577_reg_get_current_limit()
59 if ((reg_data & CHGCTRL4_MBCICHWRCL_MASK) == 0) in max14577_reg_get_current_limit()
62 reg_data = ((reg_data & CHGCTRL4_MBCICHWRCH_MASK) >> in max14577_reg_get_current_limit()
64 return limits->high_start + reg_data * limits->high_step; in max14577_reg_get_current_limit()
[all …]
Dmax77693-regulator.c71 const struct chg_reg_data *reg_data = rdev_get_drvdata(rdev); in max77693_chg_get_current_limit() local
78 ret = regmap_read(rdev->regmap, reg_data->linear_reg, &reg); in max77693_chg_get_current_limit()
82 sel = reg & reg_data->linear_mask; in max77693_chg_get_current_limit()
85 if (sel <= reg_data->min_sel) in max77693_chg_get_current_limit()
88 sel -= reg_data->min_sel; in max77693_chg_get_current_limit()
90 val = chg_min_uA + reg_data->uA_step * sel; in max77693_chg_get_current_limit()
100 const struct chg_reg_data *reg_data = rdev_get_drvdata(rdev); in max77693_chg_set_current_limit() local
104 while (chg_min_uA + reg_data->uA_step * sel < min_uA) in max77693_chg_set_current_limit()
107 if (chg_min_uA + reg_data->uA_step * sel > max_uA) in max77693_chg_set_current_limit()
111 sel += reg_data->min_sel; in max77693_chg_set_current_limit()
[all …]
Dmax8952.c177 pd->reg_data = of_get_regulator_init_data(dev, np, &regulator); in max8952_parse_dt()
178 if (!pd->reg_data) { in max8952_parse_dt()
223 config.init_data = pdata->reg_data; in max8952_pmic_probe()
230 if (pdata->reg_data->constraints.boot_on) in max8952_pmic_probe()
/drivers/net/ethernet/xilinx/
Dxilinx_emaclite.c164 u32 reg_data; in xemaclite_enable_interrupts() local
167 reg_data = xemaclite_readl(drvdata->base_addr + XEL_TSR_OFFSET); in xemaclite_enable_interrupts()
168 xemaclite_writel(reg_data | XEL_TSR_XMIT_IE_MASK, in xemaclite_enable_interrupts()
187 u32 reg_data; in xemaclite_disable_interrupts() local
193 reg_data = xemaclite_readl(drvdata->base_addr + XEL_TSR_OFFSET); in xemaclite_disable_interrupts()
194 xemaclite_writel(reg_data & (~XEL_TSR_XMIT_IE_MASK), in xemaclite_disable_interrupts()
198 reg_data = xemaclite_readl(drvdata->base_addr + XEL_RSR_OFFSET); in xemaclite_disable_interrupts()
199 xemaclite_writel(reg_data & (~XEL_RSR_RECV_IE_MASK), in xemaclite_disable_interrupts()
321 u32 reg_data; in xemaclite_send_data() local
332 reg_data = xemaclite_readl(addr + XEL_TSR_OFFSET); in xemaclite_send_data()
[all …]
/drivers/usb/isp1760/
Disp1760-if.c37 u32 reg_data; in isp1761_pci_init() local
73 reg_data = 0; in isp1761_pci_init()
74 while ((reg_data != 0xFACE) && retry_count) { in isp1761_pci_init()
80 reg_data = readl(iobase + HC_SCRATCH_REG) & 0x0000ffff; in isp1761_pci_init()
90 if (reg_data != 0xFACE) { in isp1761_pci_init()
91 dev_err(&dev->dev, "scratch register mismatch %x\n", reg_data); in isp1761_pci_init()
113 reg_data = readl(iobase + PLX_INT_CSR_REG); in isp1761_pci_init()
114 reg_data |= 0x900; in isp1761_pci_init()
115 writel(reg_data, iobase + PLX_INT_CSR_REG); in isp1761_pci_init()
/drivers/char/xilinx_hwicap/
Dfifo_icap.c359 u32 reg_data; in fifo_icap_reset() local
364 reg_data = in_be32(drvdata->base_address + XHI_CR_OFFSET); in fifo_icap_reset()
367 reg_data | XHI_CR_SW_RESET_MASK); in fifo_icap_reset()
370 reg_data & (~XHI_CR_SW_RESET_MASK)); in fifo_icap_reset()
380 u32 reg_data; in fifo_icap_flush_fifo() local
385 reg_data = in_be32(drvdata->base_address + XHI_CR_OFFSET); in fifo_icap_flush_fifo()
388 reg_data | XHI_CR_FIFO_CLR_MASK); in fifo_icap_flush_fifo()
391 reg_data & (~XHI_CR_FIFO_CLR_MASK)); in fifo_icap_flush_fifo()
/drivers/extcon/
Dextcon-sm5502.c34 struct reg_data { struct
55 struct reg_data *reg_data; member
70 static struct reg_data sm5502_reg_data[] = {
521 unsigned int reg_data, vendor_id, version_id; in sm5502_init_dev_type() local
525 ret = regmap_read(info->regmap, SM5502_REG_DEVICE_ID, &reg_data); in sm5502_init_dev_type()
532 vendor_id = ((reg_data & SM5502_REG_DEVICE_ID_VENDOR_MASK) >> in sm5502_init_dev_type()
534 version_id = ((reg_data & SM5502_REG_DEVICE_ID_VERSION_MASK) >> in sm5502_init_dev_type()
544 if (!info->reg_data[i].invert) in sm5502_init_dev_type()
545 val |= ~info->reg_data[i].val; in sm5502_init_dev_type()
547 val = info->reg_data[i].val; in sm5502_init_dev_type()
[all …]
Dextcon-rt8973a.c35 struct reg_data { struct
59 struct reg_data *reg_data; argument
75 static struct reg_data rt8973a_reg_data[] = {
528 u8 reg = info->reg_data[i].reg; in rt8973a_init_dev_type()
529 u8 mask = info->reg_data[i].mask; in rt8973a_init_dev_type()
532 if (info->reg_data[i].invert) in rt8973a_init_dev_type()
533 val = ~info->reg_data[i].val; in rt8973a_init_dev_type()
535 val = info->reg_data[i].val; in rt8973a_init_dev_type()
576 info->reg_data = rt8973a_reg_data; in rt8973a_muic_i2c_probe()
/drivers/clk/ti/
Dclkctrl.c410 const struct omap_clkctrl_reg_data *reg_data; in _ti_omap4_clkctrl_setup() local
447 reg_data = data->regs; in _ti_omap4_clkctrl_setup()
449 while (reg_data->parent) { in _ti_omap4_clkctrl_setup()
454 hw->enable_reg.ptr = provider->base + reg_data->offset; in _ti_omap4_clkctrl_setup()
456 _ti_clkctrl_setup_subclks(provider, node, reg_data, in _ti_omap4_clkctrl_setup()
459 if (reg_data->flags & CLKF_SW_SUP) in _ti_omap4_clkctrl_setup()
461 if (reg_data->flags & CLKF_HW_SUP) in _ti_omap4_clkctrl_setup()
463 if (reg_data->flags & CLKF_NO_IDLEST) in _ti_omap4_clkctrl_setup()
466 init.parent_names = &reg_data->parent; in _ti_omap4_clkctrl_setup()
471 reg_data->offset, 0); in _ti_omap4_clkctrl_setup()
[all …]
/drivers/staging/vt6656/
Drf.c604 u8 reg_data[4]; in vnt_rf_write_embedded() local
608 reg_data[0] = (u8)data; in vnt_rf_write_embedded()
609 reg_data[1] = (u8)(data >> 8); in vnt_rf_write_embedded()
610 reg_data[2] = (u8)(data >> 16); in vnt_rf_write_embedded()
611 reg_data[3] = (u8)(data >> 24); in vnt_rf_write_embedded()
614 0, 0, ARRAY_SIZE(reg_data), reg_data); in vnt_rf_write_embedded()
/drivers/clk/
Dclk-cdce925.c528 u8 reg_data[2]; in cdce925_regmap_i2c_write() local
534 reg_data[0] = CDCE925_I2C_COMMAND_BYTE_TRANSFER | ((u8 *)data)[0]; in cdce925_regmap_i2c_write()
535 reg_data[1] = ((u8 *)data)[1]; in cdce925_regmap_i2c_write()
538 reg_data[0], reg_data[1]); in cdce925_regmap_i2c_write()
540 ret = i2c_master_send(i2c, reg_data, count); in cdce925_regmap_i2c_write()
556 u8 reg_data[2]; in cdce925_regmap_i2c_read() local
563 xfer[0].buf = reg_data; in cdce925_regmap_i2c_read()
565 reg_data[0] = in cdce925_regmap_i2c_read()
569 reg_data[0] = in cdce925_regmap_i2c_read()
571 reg_data[1] = val_size; in cdce925_regmap_i2c_read()
[all …]
/drivers/input/mouse/
Dcyapa_gen3.c377 static int cyapa_gen3_state_parse(struct cyapa *cyapa, u8 *reg_data, int len) in cyapa_gen3_state_parse() argument
382 if (reg_data[REG_BL_FILE] == BL_FILE && in cyapa_gen3_state_parse()
383 reg_data[REG_BL_ERROR] == BL_ERROR_NO_ERR_IDLE && in cyapa_gen3_state_parse()
384 (reg_data[REG_BL_STATUS] == in cyapa_gen3_state_parse()
386 reg_data[REG_BL_STATUS] == BL_STATUS_RUNNING)) { in cyapa_gen3_state_parse()
394 } else if (reg_data[REG_BL_FILE] == BL_FILE && in cyapa_gen3_state_parse()
395 (reg_data[REG_BL_STATUS] & BL_STATUS_RUNNING) == in cyapa_gen3_state_parse()
398 if (reg_data[REG_BL_STATUS] & BL_STATUS_BUSY) { in cyapa_gen3_state_parse()
401 if ((reg_data[REG_BL_ERROR] & BL_ERROR_BOOTLOADING) == in cyapa_gen3_state_parse()
407 } else if ((reg_data[REG_OP_STATUS] & OP_STATUS_SRC) && in cyapa_gen3_state_parse()
[all …]
Dcyapa_gen5.c833 static int gen5_hid_description_header_parse(struct cyapa *cyapa, u8 *reg_data) in gen5_hid_description_header_parse() argument
854 if (reg_data[PIP_RESP_REPORT_ID_OFFSET] == in gen5_hid_description_header_parse()
891 static int gen5_report_data_header_parse(struct cyapa *cyapa, u8 *reg_data) in gen5_report_data_header_parse() argument
895 length = get_unaligned_le16(&reg_data[PIP_RESP_LENGTH_OFFSET]); in gen5_report_data_header_parse()
896 switch (reg_data[PIP_RESP_REPORT_ID_OFFSET]) { in gen5_report_data_header_parse()
922 static int gen5_cmd_resp_header_parse(struct cyapa *cyapa, u8 *reg_data) in gen5_cmd_resp_header_parse() argument
933 length = get_unaligned_le16(&reg_data[PIP_RESP_LENGTH_OFFSET]); in gen5_cmd_resp_header_parse()
940 if (reg_data[PIP_RESP_REPORT_ID_OFFSET] == in gen5_cmd_resp_header_parse()
976 static int cyapa_gen5_state_parse(struct cyapa *cyapa, u8 *reg_data, int len) in cyapa_gen5_state_parse() argument
980 if (!reg_data || len < 3) in cyapa_gen5_state_parse()
[all …]
/drivers/net/wireless/ath/wcn36xx/
Ddxe.c265 int reg_data = 0; in wcn36xx_dxe_enable_ch_int() local
269 &reg_data); in wcn36xx_dxe_enable_ch_int()
271 reg_data |= wcn_ch; in wcn36xx_dxe_enable_ch_int()
275 (int)reg_data); in wcn36xx_dxe_enable_ch_int()
709 int reg_data = 0, ret; in wcn36xx_dxe_init() local
711 reg_data = WCN36XX_DXE_REG_RESET; in wcn36xx_dxe_init()
712 wcn36xx_dxe_write_register(wcn, WCN36XX_DXE_REG_CSR_RESET, reg_data); in wcn36xx_dxe_init()
715 reg_data = (WCN36XX_DXE_INT_CH3_MASK | WCN36XX_DXE_INT_CH1_MASK) << 16 | in wcn36xx_dxe_init()
718 wcn36xx_ccu_write_register(wcn, WCN36XX_CCU_DXE_INT_SELECT_PRONTO, reg_data); in wcn36xx_dxe_init()
720 wcn36xx_ccu_write_register(wcn, WCN36XX_CCU_DXE_INT_SELECT_RIVA, reg_data); in wcn36xx_dxe_init()
[all …]
/drivers/pinctrl/ti/
Dpinctrl-ti-iodelay.c154 const struct ti_iodelay_reg_data *reg_data; member
209 const struct ti_iodelay_reg_data *reg = iod->reg_data; in ti_iodelay_pinconf_set()
283 const struct ti_iodelay_reg_data *reg = iod->reg_data; in ti_iodelay_pinconf_init_dev()
361 const struct ti_iodelay_reg_data *reg = iod->reg_data; in ti_iodelay_pinconf_deinit_dev()
399 const struct ti_iodelay_reg_data *r = iod->reg_data; in ti_iodelay_offset_to_pin()
439 r = iod->reg_data; in ti_iodelay_node_iterator()
643 const struct ti_iodelay_reg_data *r = iod->reg_data; in ti_iodelay_pin_to_offset()
665 r = iod->reg_data; in ti_iodelay_pin_dbg_show()
748 const struct ti_iodelay_reg_data *r = iod->reg_data; in ti_iodelay_alloc_pins()
850 iod->reg_data = match->data; in ti_iodelay_probe()
[all …]
/drivers/mfd/
Dda9150-core.c71 u8 *reg_data; in da9150_i2c_write_device() local
74 reg_data = kzalloc(1 + count, GFP_KERNEL); in da9150_i2c_write_device()
75 if (!reg_data) in da9150_i2c_write_device()
78 reg_data[0] = addr; in da9150_i2c_write_device()
79 memcpy(&reg_data[1], buf, count); in da9150_i2c_write_device()
85 xfer.buf = reg_data; in da9150_i2c_write_device()
88 kfree(reg_data); in da9150_i2c_write_device()
Dmax77843.c106 unsigned int reg_data; in max77843_probe() local
135 MAX77843_SYS_REG_PMICID, &reg_data); in max77843_probe()
140 dev_info(&i2c->dev, "device ID: 0x%x\n", reg_data); in max77843_probe()
/drivers/pinctrl/
Dpinctrl-sx150x.c90 u8 reg_data; member
165 .reg_data = 0x00,
185 .reg_data = 0x00,
208 .reg_data = 0x00,
231 .reg_data = 0x00,
250 .reg_data = 0x00,
272 .reg_data = 0x00,
295 .reg_data = 0x08,
316 .reg_data = 0x08,
337 .reg_data = 0x10,
[all …]
/drivers/media/dvb-frontends/
Dmxl5xx.c494 u32 reg_data = 0; in read_snr() local
501 &reg_data); in read_snr()
506 p->cnr.stat[0].svalue = (s16)reg_data * 10; in read_snr()
572 u32 reg_data = 0; in read_signal_strength() local
578 &reg_data); in read_signal_strength()
583 p->strength.stat[0].svalue = (s16) reg_data * 10; /* fix scale */ in read_signal_strength()
592 u32 reg_data = 0; in read_status() local
598 &reg_data); in read_status()
602 *status = (reg_data == 1) ? 0x1f : 0; in read_status()
668 u32 reg_data[MXL_DEMOD_CHAN_PARAMS_BUFF_SIZE]; in get_frontend() local
[all …]
/drivers/net/wireless/zydas/zd1211rw/
Dzd_usb.h87 struct reg_data { struct
94 struct reg_data reg_writes[0]; argument
133 struct reg_data regs[0];

123