| /drivers/clk/ux500/ |
| D | clk-sysctrl.c | 28 u8 reg_mask[SYSCTRL_MAX_NUM_PARENTS]; member
41 ret = ab8500_sysctrl_write(clk->reg_sel[0], clk->reg_mask[0], in clk_sysctrl_prepare()
53 if (ab8500_sysctrl_clear(clk->reg_sel[0], clk->reg_mask[0])) in clk_sysctrl_unprepare()
73 clk->reg_mask[old_index]); in clk_sysctrl_set_parent()
80 clk->reg_mask[index], in clk_sysctrl_set_parent()
85 clk->reg_mask[old_index], in clk_sysctrl_set_parent()
122 u8 *reg_mask, in clk_reg_sysctrl() argument
151 clk->reg_mask[0] = reg_mask[0]; in clk_reg_sysctrl()
157 clk->reg_mask[i] = reg_mask[i]; in clk_reg_sysctrl()
183 u8 reg_mask, in clk_reg_sysctrl_gate() argument
[all …]
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| D | clk.h | 67 u8 reg_mask,
76 u8 reg_mask,
87 u8 *reg_mask,
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| /drivers/irqchip/ |
| D | irq-mmp.c | 45 void __iomem *reg_mask; member
85 r = readl_relaxed(data->reg_mask) | (1 << hwirq); in icu_mask_ack_irq()
86 writel_relaxed(r, data->reg_mask); in icu_mask_ack_irq()
104 r = readl_relaxed(data->reg_mask) | (1 << hwirq); in icu_mask_irq()
105 writel_relaxed(r, data->reg_mask); in icu_mask_irq()
123 r = readl_relaxed(data->reg_mask) & ~(1 << hwirq); in icu_unmask_irq()
124 writel_relaxed(r, data->reg_mask); in icu_unmask_irq()
155 mask = readl_relaxed(data->reg_mask); in icu_mux_irq_demux()
261 icu_data[1].reg_mask = mmp_icu_base + 0x168; in mmp2_init_icu()
273 icu_data[2].reg_mask = mmp_icu_base + 0x16c; in mmp2_init_icu()
[all …]
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| D | irq-s3c24xx.c | 72 void __iomem *reg_mask; member
95 mask = readl_relaxed(intc->reg_mask); in s3c_irq_mask()
97 writel_relaxed(mask, intc->reg_mask); in s3c_irq_mask()
122 mask = readl_relaxed(intc->reg_mask); in s3c_irq_unmask()
124 writel_relaxed(mask, intc->reg_mask); in s3c_irq_unmask()
319 msk = readl_relaxed(sub_intc->reg_mask); in s3c_irq_demux()
553 intc->reg_mask = base + 0x08; in s3c24xx_init_intc()
561 intc->reg_mask = base + 0x1c; in s3c24xx_init_intc()
568 intc->reg_mask = base + 0x48; in s3c24xx_init_intc()
577 intc->reg_mask = base + 0xa4; in s3c24xx_init_intc()
[all …]
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| /drivers/net/ethernet/broadcom/bnx2x/ |
| D | bnx2x_init.h | 570 } reg_mask; /* Register mask (all valid bits) */ member
696 return bnx2x_blocks_parity_data[idx].reg_mask.e1; in bnx2x_parity_reg_mask()
698 return bnx2x_blocks_parity_data[idx].reg_mask.e1h; in bnx2x_parity_reg_mask()
700 return bnx2x_blocks_parity_data[idx].reg_mask.e2; in bnx2x_parity_reg_mask()
702 return bnx2x_blocks_parity_data[idx].reg_mask.e3; in bnx2x_parity_reg_mask()
742 u32 reg_mask = bnx2x_parity_reg_mask(bp, i); in bnx2x_clear_blocks_parity() local
744 if (reg_mask) { in bnx2x_clear_blocks_parity()
747 if (reg_val & reg_mask) in bnx2x_clear_blocks_parity()
751 reg_val & reg_mask); in bnx2x_clear_blocks_parity()
775 u32 reg_mask = bnx2x_parity_reg_mask(bp, i); in bnx2x_enable_blocks_parity() local
[all …]
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| /drivers/gpio/ |
| D | gpio-htc-egpio.c | 37 int reg_mask; member
207 reg, (egpio->cached_values >> shift) & ei->reg_mask); in egpio_set()
214 egpio_writew((egpio->cached_values >> shift) & ei->reg_mask, ei, reg); in egpio_set()
257 if (!((egpio->is_out >> shift) & ei->reg_mask)) in egpio_write_cache()
261 (egpio->cached_values >> shift) & ei->reg_mask, in egpio_write_cache()
265 & ei->reg_mask, ei, reg); in egpio_write_cache()
318 ei->reg_mask = (1 << pdata->reg_width) - 1; in egpio_probe()
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| /drivers/pinctrl/samsung/ |
| D | pinctrl-exynos.c | 57 unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset; in exynos_irq_mask() local
63 mask = readl(bank->eint_base + reg_mask); in exynos_irq_mask()
65 writel(mask, bank->eint_base + reg_mask); in exynos_irq_mask()
85 unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset; in exynos_irq_unmask() local
102 mask = readl(bank->eint_base + reg_mask); in exynos_irq_unmask()
104 writel(mask, bank->eint_base + reg_mask); in exynos_irq_unmask()
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| /drivers/pinctrl/ti/ |
| D | pinctrl-ti-iodelay.c | 216 u32 reg_mask, reg_val, tmp_val; in ti_iodelay_pinconf_set() local
235 reg_mask = reg->signature_mask; in ti_iodelay_pinconf_set()
238 reg_mask |= reg->binary_data_coarse_mask; in ti_iodelay_pinconf_set()
247 reg_mask |= reg->binary_data_fine_mask; in ti_iodelay_pinconf_set()
262 reg_mask |= reg->lock_mask; in ti_iodelay_pinconf_set()
264 r = regmap_update_bits(iod->regmap, cfg->offset, reg_mask, reg_val); in ti_iodelay_pinconf_set()
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| /drivers/pinctrl/mvebu/ |
| D | pinctrl-armada-37xx.c | 62 u32 reg_mask; member
104 .reg_mask = _mask, \
114 .reg_mask = _mask, \
124 .reg_mask = _mask, \
134 .reg_mask = _mask, \
145 .reg_mask = _mask, \
341 unsigned int mask = grp->reg_mask; in armada_37xx_pmx_set_by_name()
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| /drivers/net/ethernet/stmicro/stmmac/ |
| D | stmmac_mdio.c | 64 value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask; in stmmac_mdio_read()
106 value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask; in stmmac_mdio_write()
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| D | dwmac4_core.c | 134 value &= ~route_possibilities[packet - 1].reg_mask; in dwmac4_tx_queue_routing()
136 route_possibilities[packet - 1].reg_mask; in dwmac4_tx_queue_routing()
784 mac->mii.reg_mask = GENMASK(20, 16); in dwmac4_setup()
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| D | common.h | 566 unsigned int reg_mask; /* MII reg mask */ member
602 u32 reg_mask; member
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| D | dwmac100_core.c | 199 mac->mii.reg_mask = 0x000007C0; in dwmac100_setup()
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| D | dwmac1000_core.c | 562 mac->mii.reg_mask = 0x000007C0; in dwmac1000_setup()
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| D | dwmac-sun8i.c | 878 mac->mii.reg_mask = GENMASK(8, 4); in sun8i_dwmac_setup()
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| /drivers/video/fbdev/via/ |
| D | hw.c | 983 int reg_mask; in viafb_load_reg() local
992 reg_mask = 0; in viafb_load_reg()
1001 reg_mask = reg_mask | (BIT0 << j); in viafb_load_reg()
1008 viafb_write_reg_mask(cr_index, VIACR, data, reg_mask); in viafb_load_reg()
1010 viafb_write_reg_mask(cr_index, VIASR, data, reg_mask); in viafb_load_reg()
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| /drivers/phy/broadcom/ |
| D | phy-bcm-ns2-usbdrd.c | 87 static inline int pll_lock_stat(u32 usb_reg, int reg_mask, in pll_lock_stat() argument
96 if (val & reg_mask) in pll_lock_stat()
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| /drivers/gpu/drm/amd/amdgpu/ |
| D | vi.c | 797 u32 reg_mask; in vi_set_vce_clocks() local
803 reg_mask = CG_ECLK_CNTL__ECLK_DIVIDER_MASK; in vi_set_vce_clocks()
808 reg_mask = CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK | CG_ECLK_CNTL__ECLK_DIVIDER_MASK; in vi_set_vce_clocks()
827 tmp &= ~reg_mask; in vi_set_vce_clocks()
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| /drivers/crypto/qat/qat_common/ |
| D | qat_hal.c | 1229 unsigned short reg_mask; in qat_hal_put_rel_wr_xfer() local
1247 reg_mask = (unsigned short)~0x1f; in qat_hal_put_rel_wr_xfer()
1249 reg_mask = (unsigned short)~0xf; in qat_hal_put_rel_wr_xfer()
1251 if (reg_num & reg_mask) in qat_hal_put_rel_wr_xfer()
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| /drivers/hwmon/ |
| D | adt7470.c | 331 int reg_mask; in adt7470_update_device() local
337 reg_mask = ADT7470_PWM2_AUTO_MASK; in adt7470_update_device()
339 reg_mask = ADT7470_PWM1_AUTO_MASK; in adt7470_update_device()
342 if (i2c_smbus_read_byte_data(client, reg) & reg_mask) in adt7470_update_device()
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| /drivers/pinctrl/bcm/ |
| D | pinctrl-bcm281xx.c | 971 static inline void bcm281xx_pin_update(u32 *reg_val, u32 *reg_mask, in bcm281xx_pin_update() argument
977 *reg_mask |= param_mask; in bcm281xx_pin_update()
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| /drivers/media/i2c/ |
| D | mt9m111.c | 136 #define reg_mask(reg, val, mask) mt9m111_reg_mask(client, MT9M111_##reg, \ macro
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| /drivers/net/wireless/marvell/mwifiex/ |
| D | sta_cmd.c | 2043 cmd_ptr->params.reg_mask.action = cpu_to_le16(cmd_action); in mwifiex_sta_prepare_cmd()
2044 cmd_ptr->params.reg_mask.mask = cpu_to_le32( in mwifiex_sta_prepare_cmd()
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| D | fw.h | 2328 struct host_cmd_ds_mgmt_frame_reg reg_mask; member
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