/drivers/gpu/drm/amd/powerplay/smumgr/ |
D | smu7_smumgr.c | 404 if (smu_data->soft_regs_start) in smu7_request_smu_load_fw() 406 smu_data->soft_regs_start + smum_get_offsetof(smumgr, in smu7_request_smu_load_fw() 491 smu_data->soft_regs_start + smum_get_offsetof(smumgr, in smu7_check_fw_load_finish()
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D | smu7_smumgr.h | 51 uint32_t soft_regs_start; member
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D | fiji_smumgr.c | 337 &(priv->smu7_data.soft_regs_start), 0x40000); in fiji_start_smu()
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D | polaris10_smumgr.c | 346 &(smu_data->smu7_data.soft_regs_start), 0x40000); in polaris10_start_smu()
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D | polaris10_smc.c | 1471 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, smu_data->smu7_data.soft_regs_start + in polaris10_populate_vr_config() 2287 data->soft_regs_start = tmp; in polaris10_process_firmware_header() 2288 smu_data->smu7_data.soft_regs_start = tmp; in polaris10_process_firmware_header()
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D | iceland_smc.c | 2208 data->soft_regs_start = tmp; in iceland_process_firmware_header() 2209 smu7_data->soft_regs_start = tmp; in iceland_process_firmware_header()
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D | fiji_smc.c | 2397 data->soft_regs_start = tmp; in fiji_process_firmware_header() 2398 smu_data->smu7_data.soft_regs_start = tmp; in fiji_process_firmware_header()
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D | tonga_smc.c | 2869 data->soft_regs_start = tmp; in tonga_process_firmware_header() 2870 smu_data->smu7_data.soft_regs_start = tmp; in tonga_process_firmware_header()
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/drivers/gpu/drm/radeon/ |
D | si_dpm.h | 178 u32 soft_regs_start; member
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D | kv_dpm.h | 123 u32 soft_regs_start; member
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D | ci_dpm.h | 218 u32 soft_regs_start; member
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D | rv770_dpm.h | 135 u16 soft_regs_start; member
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D | rv770_dpm.c | 241 pi->soft_regs_start + reg_offset, 252 pi->soft_regs_start + reg_offset, in rv770_write_smc_soft_register() 2427 pi->soft_regs_start = RV770_SMC_SOFT_REGISTERS_START; in rv770_dpm_init()
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D | kv_dpm.c | 472 pi->soft_regs_start = tmp; in kv_process_firmware_header() 1338 return kv_copy_bytes_to_smc(rdev, pi->soft_regs_start + reg_offset, 1347 return kv_read_smc_sram_dword(rdev, pi->soft_regs_start + reg_offset,
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D | ci_dpm.c | 1284 pi->soft_regs_start + reg_offset, 1295 pi->soft_regs_start + reg_offset, in ci_write_smc_soft_register() 1814 pi->soft_regs_start = tmp; in ci_process_firmware_header()
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D | si_dpm.c | 3188 si_pi->soft_regs_start + reg_offset, value, 3199 si_pi->soft_regs_start + reg_offset, in si_write_smc_soft_register() 3498 si_pi->soft_regs_start = tmp; in si_process_firmware_header()
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D | cypress_dpm.c | 1714 pi->soft_regs_start = (u16)tmp; in cypress_get_table_locations()
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/drivers/gpu/drm/amd/powerplay/hwmgr/ |
D | rv_hwmgr.h | 245 uint32_t soft_regs_start; member
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D | smu7_hwmgr.h | 231 uint32_t soft_regs_start; member
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D | cz_hwmgr.h | 265 uint32_t soft_regs_start; member
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D | smu7_hwmgr.c | 930 uint32_t handshake_disables_offset = data->soft_regs_start in smu7_disable_handshake_uvd() 995 data->soft_regs_start + in smu7_start_dpm() 3371 offset = data->soft_regs_start + smum_get_offsetof(hwmgr->smumgr, in smu7_read_sensor() 3985 data->soft_regs_start + smum_get_offsetof(hwmgr->smumgr, in smu7_program_display_gap() 3990 data->soft_regs_start + smum_get_offsetof(hwmgr->smumgr, in smu7_program_display_gap()
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/drivers/gpu/drm/amd/amdgpu/ |
D | kv_dpm.h | 149 u32 soft_regs_start; member
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D | ci_dpm.h | 220 u32 soft_regs_start; member
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D | si_dpm.h | 592 u16 soft_regs_start; member 985 u32 soft_regs_start; member
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D | kv_dpm.c | 602 pi->soft_regs_start = tmp; in kv_process_firmware_header() 1405 return amdgpu_kv_copy_bytes_to_smc(adev, pi->soft_regs_start + reg_offset, 1414 return amdgpu_kv_read_smc_sram_dword(adev, pi->soft_regs_start + reg_offset,
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