| /drivers/media/tuners/ |
| D | tda18271-maps.c | 31 u8 val; member
202 { .rfmax = 62000, .val = 0x00 },
203 { .rfmax = 84000, .val = 0x01 },
204 { .rfmax = 100000, .val = 0x02 },
205 { .rfmax = 140000, .val = 0x03 },
206 { .rfmax = 170000, .val = 0x04 },
207 { .rfmax = 180000, .val = 0x05 },
208 { .rfmax = 865000, .val = 0x06 },
209 { .rfmax = 0, .val = 0x00 }, /* end */
213 { .rfmax = 61100, .val = 0x74 },
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| /drivers/net/ethernet/neterion/vxge/ |
| D | vxge-reg.h | 25 #define vxge_vBIT(val, loc, sz) (((u64)(val)) << (64-(loc)-(sz))) argument
26 #define vxge_vBIT32(val, loc, sz) (((u32)(val)) << (32-(loc)-(sz))) argument
54 #define VXGE_EPROM_IMG_MAJOR(val) (u32) vxge_bVALn(val, 48, 4) argument
55 #define VXGE_EPROM_IMG_MINOR(val) (u32) vxge_bVALn(val, 52, 4) argument
56 #define VXGE_EPROM_IMG_FIX(val) (u32) vxge_bVALn(val, 56, 4) argument
57 #define VXGE_EPROM_IMG_BUILD(val) (u32) vxge_bVALn(val, 60, 4) argument
59 #define VXGE_HW_GET_EPROM_IMAGE_INDEX(val) vxge_bVALn(val, 16, 8) argument
60 #define VXGE_HW_GET_EPROM_IMAGE_VALID(val) vxge_bVALn(val, 31, 1) argument
61 #define VXGE_HW_GET_EPROM_IMAGE_TYPE(val) vxge_bVALn(val, 40, 8) argument
62 #define VXGE_HW_GET_EPROM_IMAGE_REV(val) vxge_bVALn(val, 48, 16) argument
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| /drivers/hwtracing/coresight/ |
| D | coresight-etm-cp14.c | 22 int etm_readl_cp14(u32 reg, unsigned int *val) in etm_readl_cp14() argument
26 *val = etm_read(ETMCR); in etm_readl_cp14()
29 *val = etm_read(ETMCCR); in etm_readl_cp14()
32 *val = etm_read(ETMTRIGGER); in etm_readl_cp14()
35 *val = etm_read(ETMSR); in etm_readl_cp14()
38 *val = etm_read(ETMSCR); in etm_readl_cp14()
41 *val = etm_read(ETMTSSCR); in etm_readl_cp14()
44 *val = etm_read(ETMTEEVR); in etm_readl_cp14()
47 *val = etm_read(ETMTECR1); in etm_readl_cp14()
50 *val = etm_read(ETMFFLR); in etm_readl_cp14()
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| /drivers/net/wireless/broadcom/brcm80211/brcmsmac/ |
| D | types.h | 133 #define CONF_HAS(config, val) ((config) & (1 << (val))) argument
138 #define CONF_IS(config, val) ((config) == (1 << (val))) argument
139 #define CONF_GE(config, val) ((config) & (0-(1 << (val)))) argument
140 #define CONF_GT(config, val) ((config) & (0-2*(1 << (val)))) argument
141 #define CONF_LT(config, val) ((config) & ((1 << (val))-1)) argument
142 #define CONF_LE(config, val) ((config) & (2*(1 << (val))-1)) argument
146 #define NCONF_HAS(val) CONF_HAS(NCONF, val) argument
148 #define NCONF_IS(val) CONF_IS(NCONF, val) argument
149 #define NCONF_GE(val) CONF_GE(NCONF, val) argument
150 #define NCONF_GT(val) CONF_GT(NCONF, val) argument
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| /drivers/gpu/drm/msm/adreno/ |
| D | a2xx.xml.h | 265 static inline uint32_t A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) in A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR() argument
267 …return ((val) << A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHA… in A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR()
271 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) in A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR() argument
273 …return ((val) << A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHA… in A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR()
277 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) in A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR() argument
279 …return ((val) << A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BE… in A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR()
283 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) in A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR() argument
285 …return ((val) << A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BE… in A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR()
289 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) in A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR() argument
291 …return ((val) << A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BE… in A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR()
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| D | a3xx.xml.h | 944 static inline uint32_t A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES(uint32_t val) in A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES() argument
946 …return ((val) << A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES__SHIFT) & A3XX_GRAS_CL_CLIP_CNTL_NUM_… in A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES()
952 static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val) in A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ() argument
954 return ((val) << A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT) & A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK; in A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ()
958 static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val) in A3XX_GRAS_CL_GB_CLIP_ADJ_VERT() argument
960 return ((val) << A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT) & A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK; in A3XX_GRAS_CL_GB_CLIP_ADJ_VERT()
966 static inline uint32_t A3XX_GRAS_CL_VPORT_XOFFSET(float val) in A3XX_GRAS_CL_VPORT_XOFFSET() argument
968 return ((fui(val)) << A3XX_GRAS_CL_VPORT_XOFFSET__SHIFT) & A3XX_GRAS_CL_VPORT_XOFFSET__MASK; in A3XX_GRAS_CL_VPORT_XOFFSET()
974 static inline uint32_t A3XX_GRAS_CL_VPORT_XSCALE(float val) in A3XX_GRAS_CL_VPORT_XSCALE() argument
976 return ((fui(val)) << A3XX_GRAS_CL_VPORT_XSCALE__SHIFT) & A3XX_GRAS_CL_VPORT_XSCALE__MASK; in A3XX_GRAS_CL_VPORT_XSCALE()
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| D | adreno_pm4.xml.h | 314 static inline uint32_t CP_LOAD_STATE_0_DST_OFF(uint32_t val) in CP_LOAD_STATE_0_DST_OFF() argument
316 return ((val) << CP_LOAD_STATE_0_DST_OFF__SHIFT) & CP_LOAD_STATE_0_DST_OFF__MASK; in CP_LOAD_STATE_0_DST_OFF()
320 static inline uint32_t CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val) in CP_LOAD_STATE_0_STATE_SRC() argument
322 return ((val) << CP_LOAD_STATE_0_STATE_SRC__SHIFT) & CP_LOAD_STATE_0_STATE_SRC__MASK; in CP_LOAD_STATE_0_STATE_SRC()
326 static inline uint32_t CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val) in CP_LOAD_STATE_0_STATE_BLOCK() argument
328 return ((val) << CP_LOAD_STATE_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE_0_STATE_BLOCK__MASK; in CP_LOAD_STATE_0_STATE_BLOCK()
332 static inline uint32_t CP_LOAD_STATE_0_NUM_UNIT(uint32_t val) in CP_LOAD_STATE_0_NUM_UNIT() argument
334 return ((val) << CP_LOAD_STATE_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE_0_NUM_UNIT__MASK; in CP_LOAD_STATE_0_NUM_UNIT()
340 static inline uint32_t CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val) in CP_LOAD_STATE_1_STATE_TYPE() argument
342 return ((val) << CP_LOAD_STATE_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE_1_STATE_TYPE__MASK; in CP_LOAD_STATE_1_STATE_TYPE()
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| D | a4xx.xml.h | 851 static inline uint32_t A4XX_CGC_HLSQ_EARLY_CYC(uint32_t val) in A4XX_CGC_HLSQ_EARLY_CYC() argument
853 return ((val) << A4XX_CGC_HLSQ_EARLY_CYC__SHIFT) & A4XX_CGC_HLSQ_EARLY_CYC__MASK; in A4XX_CGC_HLSQ_EARLY_CYC()
908 static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val) in A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH() argument
910 …return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_WID… in A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH()
914 static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val) in A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT() argument
916 …return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_HE… in A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT()
930 static inline uint32_t A4XX_RB_MODE_CONTROL_WIDTH(uint32_t val) in A4XX_RB_MODE_CONTROL_WIDTH() argument
932 return ((val >> 5) << A4XX_RB_MODE_CONTROL_WIDTH__SHIFT) & A4XX_RB_MODE_CONTROL_WIDTH__MASK; in A4XX_RB_MODE_CONTROL_WIDTH()
936 static inline uint32_t A4XX_RB_MODE_CONTROL_HEIGHT(uint32_t val) in A4XX_RB_MODE_CONTROL_HEIGHT() argument
938 return ((val >> 5) << A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT) & A4XX_RB_MODE_CONTROL_HEIGHT__MASK; in A4XX_RB_MODE_CONTROL_HEIGHT()
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| D | a5xx.xml.h | 1001 static inline uint32_t A5XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val) in A5XX_CP_PROTECT_REG_BASE_ADDR() argument
1003 return ((val) << A5XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A5XX_CP_PROTECT_REG_BASE_ADDR__MASK; in A5XX_CP_PROTECT_REG_BASE_ADDR()
1007 static inline uint32_t A5XX_CP_PROTECT_REG_MASK_LEN(uint32_t val) in A5XX_CP_PROTECT_REG_MASK_LEN() argument
1009 return ((val) << A5XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A5XX_CP_PROTECT_REG_MASK_LEN__MASK; in A5XX_CP_PROTECT_REG_MASK_LEN()
1914 static inline uint32_t A5XX_VSC_BIN_SIZE_WIDTH(uint32_t val) in A5XX_VSC_BIN_SIZE_WIDTH() argument
1916 return ((val >> 5) << A5XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A5XX_VSC_BIN_SIZE_WIDTH__MASK; in A5XX_VSC_BIN_SIZE_WIDTH()
1920 static inline uint32_t A5XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) in A5XX_VSC_BIN_SIZE_HEIGHT() argument
1922 return ((val >> 5) << A5XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A5XX_VSC_BIN_SIZE_HEIGHT__MASK; in A5XX_VSC_BIN_SIZE_HEIGHT()
1938 static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_X(uint32_t val) in A5XX_VSC_PIPE_CONFIG_REG_X() argument
1940 return ((val) << A5XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_X__MASK; in A5XX_VSC_PIPE_CONFIG_REG_X()
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| /drivers/phy/ |
| D | phy-xgene.c | 566 u32 val; in sds_wr() local
576 val = readl(csr_base + indirect_cmd_reg); in sds_wr()
577 } while (!(val & CFG_IND_CMD_DONE_MASK) && in sds_wr()
579 if (!(val & CFG_IND_CMD_DONE_MASK)) in sds_wr()
588 u32 val; in sds_rd() local
596 val = readl(csr_base + indirect_cmd_reg); in sds_rd()
597 } while (!(val & CFG_IND_CMD_DONE_MASK) && in sds_rd()
600 if (!(val & CFG_IND_CMD_DONE_MASK)) in sds_rd()
609 u32 val; in cmu_wr() local
618 SATA_ENET_SDS_IND_RDATA_REG, reg, &val); in cmu_wr()
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| /drivers/gpu/drm/msm/dsi/ |
| D | dsi.xml.h | 113 static inline uint32_t DSI_6G_HW_VERSION_MAJOR(uint32_t val) in DSI_6G_HW_VERSION_MAJOR() argument
115 return ((val) << DSI_6G_HW_VERSION_MAJOR__SHIFT) & DSI_6G_HW_VERSION_MAJOR__MASK; in DSI_6G_HW_VERSION_MAJOR()
119 static inline uint32_t DSI_6G_HW_VERSION_MINOR(uint32_t val) in DSI_6G_HW_VERSION_MINOR() argument
121 return ((val) << DSI_6G_HW_VERSION_MINOR__SHIFT) & DSI_6G_HW_VERSION_MINOR__MASK; in DSI_6G_HW_VERSION_MINOR()
125 static inline uint32_t DSI_6G_HW_VERSION_STEP(uint32_t val) in DSI_6G_HW_VERSION_STEP() argument
127 return ((val) << DSI_6G_HW_VERSION_STEP__SHIFT) & DSI_6G_HW_VERSION_STEP__MASK; in DSI_6G_HW_VERSION_STEP()
156 static inline uint32_t DSI_VID_CFG0_VIRT_CHANNEL(uint32_t val) in DSI_VID_CFG0_VIRT_CHANNEL() argument
158 return ((val) << DSI_VID_CFG0_VIRT_CHANNEL__SHIFT) & DSI_VID_CFG0_VIRT_CHANNEL__MASK; in DSI_VID_CFG0_VIRT_CHANNEL()
162 static inline uint32_t DSI_VID_CFG0_DST_FORMAT(enum dsi_vid_dst_format val) in DSI_VID_CFG0_DST_FORMAT() argument
164 return ((val) << DSI_VID_CFG0_DST_FORMAT__SHIFT) & DSI_VID_CFG0_DST_FORMAT__MASK; in DSI_VID_CFG0_DST_FORMAT()
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| /drivers/net/wireless/ath/ath5k/ |
| D | eeprom.c | 43 u16 val; in ath5k_eeprom_bin2freq() local
50 val = (5 * bin) + 4800; in ath5k_eeprom_bin2freq()
52 val = bin > 62 ? (10 * 62) + (5 * (bin - 62)) + 5100 : in ath5k_eeprom_bin2freq()
56 val = bin + 2300; in ath5k_eeprom_bin2freq()
58 val = bin + 2400; in ath5k_eeprom_bin2freq()
61 return val; in ath5k_eeprom_bin2freq()
76 u16 val; in ath5k_eeprom_init_header() local
96 AR5K_EEPROM_READ(AR5K_EEPROM_SIZE_UPPER, val); in ath5k_eeprom_init_header()
97 if (val) { in ath5k_eeprom_init_header()
98 eep_max = (val & AR5K_EEPROM_SIZE_UPPER_MASK) << in ath5k_eeprom_init_header()
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| /drivers/net/ethernet/chelsio/cxgb4/ |
| D | cxgb4_tc_u32_parse.h | 41 int (*val)(struct ch_filter_specification *f, u32 val, u32 mask); member
46 u32 val, u32 mask) in cxgb4_fill_ipv4_tos() argument
48 f->val.tos = (ntohl(val) >> 16) & 0x000000FF; in cxgb4_fill_ipv4_tos()
55 u32 val, u32 mask) in cxgb4_fill_ipv4_frag() argument
60 frag_val = (ntohl(val) >> 13) & 0x00000007; in cxgb4_fill_ipv4_frag()
64 f->val.frag = 1; in cxgb4_fill_ipv4_frag()
67 f->val.frag = 0; in cxgb4_fill_ipv4_frag()
77 u32 val, u32 mask) in cxgb4_fill_ipv4_proto() argument
79 f->val.proto = (ntohl(val) >> 16) & 0x000000FF; in cxgb4_fill_ipv4_proto()
86 u32 val, u32 mask) in cxgb4_fill_ipv4_src_ip() argument
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| /drivers/phy/marvell/ |
| D | phy-mvebu-cp110-comphy.c | 192 u32 val; in mvebu_comphy_ethernet_init_reset() local
194 regmap_read(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), &val); in mvebu_comphy_ethernet_init_reset()
195 val &= ~MVEBU_COMPHY_CONF1_USB_PCIE; in mvebu_comphy_ethernet_init_reset()
196 val |= MVEBU_COMPHY_CONF1_PWRUP; in mvebu_comphy_ethernet_init_reset()
197 regmap_write(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), val); in mvebu_comphy_ethernet_init_reset()
200 val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id)); in mvebu_comphy_ethernet_init_reset()
201 val &= ~(MVEBU_COMPHY_SERDES_CFG0_PU_PLL | in mvebu_comphy_ethernet_init_reset()
208 val |= MVEBU_COMPHY_SERDES_CFG0_GEN_RX(0xe) | in mvebu_comphy_ethernet_init_reset()
211 val |= MVEBU_COMPHY_SERDES_CFG0_GEN_RX(0x6) | in mvebu_comphy_ethernet_init_reset()
214 writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id)); in mvebu_comphy_ethernet_init_reset()
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| /drivers/usb/phy/ |
| D | phy-tegra-usb.c | 209 unsigned long val; in set_pts() local
212 val = readl(base + TEGRA_USB_HOSTPC1_DEVLC); in set_pts()
213 val &= ~TEGRA_USB_HOSTPC1_DEVLC_PTS(~0); in set_pts()
214 val |= TEGRA_USB_HOSTPC1_DEVLC_PTS(pts_val); in set_pts()
215 writel(val, base + TEGRA_USB_HOSTPC1_DEVLC); in set_pts()
217 val = readl(base + TEGRA_USB_PORTSC1) & ~TEGRA_PORTSC1_RWC_BITS; in set_pts()
218 val &= ~TEGRA_USB_PORTSC1_PTS(~0); in set_pts()
219 val |= TEGRA_USB_PORTSC1_PTS(pts_val); in set_pts()
220 writel(val, base + TEGRA_USB_PORTSC1); in set_pts()
227 unsigned long val; in set_phcd() local
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| /drivers/gpu/drm/msm/mdp/mdp4/ |
| D | mdp4.xml.h | 113 static inline uint32_t MDP4_VERSION_MINOR(uint32_t val) in MDP4_VERSION_MINOR() argument
115 return ((val) << MDP4_VERSION_MINOR__SHIFT) & MDP4_VERSION_MINOR__MASK; in MDP4_VERSION_MINOR()
119 static inline uint32_t MDP4_VERSION_MAJOR(uint32_t val) in MDP4_VERSION_MAJOR() argument
121 return ((val) << MDP4_VERSION_MAJOR__SHIFT) & MDP4_VERSION_MAJOR__MASK; in MDP4_VERSION_MAJOR()
141 static inline uint32_t MDP4_DISP_INTF_SEL_PRIM(enum mdp4_intf val) in MDP4_DISP_INTF_SEL_PRIM() argument
143 return ((val) << MDP4_DISP_INTF_SEL_PRIM__SHIFT) & MDP4_DISP_INTF_SEL_PRIM__MASK; in MDP4_DISP_INTF_SEL_PRIM()
147 static inline uint32_t MDP4_DISP_INTF_SEL_SEC(enum mdp4_intf val) in MDP4_DISP_INTF_SEL_SEC() argument
149 return ((val) << MDP4_DISP_INTF_SEL_SEC__SHIFT) & MDP4_DISP_INTF_SEL_SEC__MASK; in MDP4_DISP_INTF_SEL_SEC()
153 static inline uint32_t MDP4_DISP_INTF_SEL_EXT(enum mdp4_intf val) in MDP4_DISP_INTF_SEL_EXT() argument
155 return ((val) << MDP4_DISP_INTF_SEL_EXT__SHIFT) & MDP4_DISP_INTF_SEL_EXT__MASK; in MDP4_DISP_INTF_SEL_EXT()
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| /drivers/net/phy/ |
| D | bcm-phy-lib.c | 25 int bcm_phy_write_exp(struct phy_device *phydev, u16 reg, u16 val) in bcm_phy_write_exp() argument
33 return phy_write(phydev, MII_BCM54XX_EXP_DATA, val); in bcm_phy_write_exp()
39 int val; in bcm_phy_read_exp() local
41 val = phy_write(phydev, MII_BCM54XX_EXP_SEL, reg); in bcm_phy_read_exp()
42 if (val < 0) in bcm_phy_read_exp()
43 return val; in bcm_phy_read_exp()
45 val = phy_read(phydev, MII_BCM54XX_EXP_DATA); in bcm_phy_read_exp()
50 return val; in bcm_phy_read_exp()
65 int bcm54xx_auxctl_write(struct phy_device *phydev, u16 regnum, u16 val) in bcm54xx_auxctl_write() argument
67 return phy_write(phydev, MII_BCM54XX_AUX_CTL, regnum | val); in bcm54xx_auxctl_write()
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| D | marvell10g.c | 47 int old, val, ret; in mv3310_modify() local
53 val = (old & ~mask) | (bits & mask); in mv3310_modify()
54 if (val == old) in mv3310_modify()
57 ret = phy_write_mmd(phydev, devad, reg, val); in mv3310_modify()
97 int val; in mv3310_config_init() local
111 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); in mv3310_config_init()
112 if (val < 0) in mv3310_config_init()
113 return val; in mv3310_config_init()
115 if (val & MDIO_AN_STAT1_ABLE) in mv3310_config_init()
119 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT2); in mv3310_config_init()
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| /drivers/gpu/drm/msm/mdp/mdp5/ |
| D | mdp5.xml.h | 180 static inline uint32_t MDSS_HW_VERSION_STEP(uint32_t val) in MDSS_HW_VERSION_STEP() argument
182 return ((val) << MDSS_HW_VERSION_STEP__SHIFT) & MDSS_HW_VERSION_STEP__MASK; in MDSS_HW_VERSION_STEP()
186 static inline uint32_t MDSS_HW_VERSION_MINOR(uint32_t val) in MDSS_HW_VERSION_MINOR() argument
188 return ((val) << MDSS_HW_VERSION_MINOR__SHIFT) & MDSS_HW_VERSION_MINOR__MASK; in MDSS_HW_VERSION_MINOR()
192 static inline uint32_t MDSS_HW_VERSION_MAJOR(uint32_t val) in MDSS_HW_VERSION_MAJOR() argument
194 return ((val) << MDSS_HW_VERSION_MAJOR__SHIFT) & MDSS_HW_VERSION_MAJOR__MASK; in MDSS_HW_VERSION_MAJOR()
207 static inline uint32_t MDP5_HW_VERSION_STEP(uint32_t val) in MDP5_HW_VERSION_STEP() argument
209 return ((val) << MDP5_HW_VERSION_STEP__SHIFT) & MDP5_HW_VERSION_STEP__MASK; in MDP5_HW_VERSION_STEP()
213 static inline uint32_t MDP5_HW_VERSION_MINOR(uint32_t val) in MDP5_HW_VERSION_MINOR() argument
215 return ((val) << MDP5_HW_VERSION_MINOR__SHIFT) & MDP5_HW_VERSION_MINOR__MASK; in MDP5_HW_VERSION_MINOR()
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| /drivers/gpu/drm/i915/ |
| D | intel_dpio_phy.c | 267 u32 val; in bxt_ddi_phy_set_signal_level() local
277 val = I915_READ(BXT_PORT_PCS_DW10_LN01(phy, ch)); in bxt_ddi_phy_set_signal_level()
278 val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT); in bxt_ddi_phy_set_signal_level()
279 I915_WRITE(BXT_PORT_PCS_DW10_GRP(phy, ch), val); in bxt_ddi_phy_set_signal_level()
281 val = I915_READ(BXT_PORT_TX_DW2_LN0(phy, ch)); in bxt_ddi_phy_set_signal_level()
282 val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE); in bxt_ddi_phy_set_signal_level()
283 val |= margin << MARGIN_000_SHIFT | scale << UNIQ_TRANS_SCALE_SHIFT; in bxt_ddi_phy_set_signal_level()
284 I915_WRITE(BXT_PORT_TX_DW2_GRP(phy, ch), val); in bxt_ddi_phy_set_signal_level()
286 val = I915_READ(BXT_PORT_TX_DW3_LN0(phy, ch)); in bxt_ddi_phy_set_signal_level()
287 val &= ~SCALE_DCOMP_METHOD; in bxt_ddi_phy_set_signal_level()
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| /drivers/hwmon/ |
| D | hwmon-vid.c | 82 int vid_from_reg(int val, u8 vrm) in vid_from_reg() argument
90 val &= 0x3f; in vid_from_reg()
91 if ((val & 0x1f) == 0x1f) in vid_from_reg()
93 if ((val & 0x1f) <= 0x09 || val == 0x0a) in vid_from_reg()
94 vid = 1087500 - (val & 0x1f) * 25000; in vid_from_reg()
96 vid = 1862500 - (val & 0x1f) * 25000; in vid_from_reg()
97 if (val & 0x20) in vid_from_reg()
103 val &= 0xff; in vid_from_reg()
104 if (val < 0x02 || val > 0xb2) in vid_from_reg()
106 return (1600000 - (val - 2) * 6250 + 500) / 1000; in vid_from_reg()
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| D | lm90.c | 612 int val; in lm90_update_limits() local
614 val = lm90_read_reg(client, LM90_REG_R_LOCAL_CRIT); in lm90_update_limits()
615 if (val < 0) in lm90_update_limits()
616 return val; in lm90_update_limits()
617 data->temp8[LOCAL_CRIT] = val; in lm90_update_limits()
619 val = lm90_read_reg(client, LM90_REG_R_REMOTE_CRIT); in lm90_update_limits()
620 if (val < 0) in lm90_update_limits()
621 return val; in lm90_update_limits()
622 data->temp8[REMOTE_CRIT] = val; in lm90_update_limits()
624 val = lm90_read_reg(client, LM90_REG_R_TCRIT_HYST); in lm90_update_limits()
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| /drivers/spi/ |
| D | spi-armada-3700.c | 130 u32 val; in a3700_spi_auto_cs_unset() local
132 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); in a3700_spi_auto_cs_unset()
133 val &= ~A3700_SPI_AUTO_CS; in a3700_spi_auto_cs_unset()
134 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); in a3700_spi_auto_cs_unset()
139 u32 val; in a3700_spi_activate_cs() local
141 val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); in a3700_spi_activate_cs()
142 val |= (A3700_SPI_EN << cs); in a3700_spi_activate_cs()
143 spireg_write(a3700_spi, A3700_SPI_IF_CTRL_REG, val); in a3700_spi_activate_cs()
149 u32 val; in a3700_spi_deactivate_cs() local
151 val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); in a3700_spi_deactivate_cs()
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| /drivers/media/dvb-frontends/ |
| D | lgdt3306a.c | 120 static int lgdt3306a_write_reg(struct lgdt3306a_state *state, u16 reg, u8 val) in lgdt3306a_write_reg() argument
123 u8 buf[] = { reg >> 8, reg & 0xff, val }; in lgdt3306a_write_reg()
129 dbg_reg("reg: 0x%04x, val: 0x%02x\n", reg, val); in lgdt3306a_write_reg()
144 static int lgdt3306a_read_reg(struct lgdt3306a_state *state, u16 reg, u8 *val) in lgdt3306a_read_reg() argument
152 .flags = I2C_M_RD, .buf = val, .len = 1 }, in lgdt3306a_read_reg()
165 dbg_reg("reg: 0x%04x, val: 0x%02x\n", reg, *val); in lgdt3306a_read_reg()
182 u8 val; in lgdt3306a_set_reg_bit() local
187 ret = lgdt3306a_read_reg(state, reg, &val); in lgdt3306a_set_reg_bit()
191 val &= ~(1 << bit); in lgdt3306a_set_reg_bit()
192 val |= (onoff & 1) << bit; in lgdt3306a_set_reg_bit()
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| /drivers/gpu/drm/rockchip/ |
| D | cdn-dp-reg.c | 39 u32 val; in cdn_dp_clock_reset() local
41 val = DPTX_FRMR_DATA_CLK_RSTN_EN | in cdn_dp_clock_reset()
53 writel(val, dp->regs + SOURCE_DPTX_CAR); in cdn_dp_clock_reset()
55 val = SOURCE_PHY_RSTN_EN | SOURCE_PHY_CLK_EN; in cdn_dp_clock_reset()
56 writel(val, dp->regs + SOURCE_PHY_CAR); in cdn_dp_clock_reset()
58 val = SOURCE_PKT_SYS_RSTN_EN | in cdn_dp_clock_reset()
62 writel(val, dp->regs + SOURCE_PKT_CAR); in cdn_dp_clock_reset()
64 val = SPDIF_CDR_CLK_RSTN_EN | in cdn_dp_clock_reset()
70 writel(val, dp->regs + SOURCE_AIF_CAR); in cdn_dp_clock_reset()
72 val = SOURCE_CIPHER_SYSTEM_CLK_RSTN_EN | in cdn_dp_clock_reset()
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