| /drivers/gpu/drm/radeon/ |
| D | rs780_dpm.c | 570 if ((new_ps->vclk == old_ps->vclk) && in rs780_set_uvd_clock_before_set_eng_clock()
577 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rs780_set_uvd_clock_before_set_eng_clock()
587 if ((new_ps->vclk == old_ps->vclk) && in rs780_set_uvd_clock_after_set_eng_clock()
594 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rs780_set_uvd_clock_after_set_eng_clock()
727 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); in rs780_parse_pplib_non_clock_info()
730 rps->vclk = 0; in rs780_parse_pplib_non_clock_info()
735 if ((rps->vclk == 0) || (rps->dclk == 0)) { in rs780_parse_pplib_non_clock_info()
736 rps->vclk = RS780_DEFAULT_VCLK_FREQ; in rs780_parse_pplib_non_clock_info()
944 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rs780_dpm_print_power_state()
993 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rs780_dpm_debugfs_print_current_performance_level()
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| D | trinity_dpm.c | 897 if ((rps->vclk == 0) && (rps->dclk == 0)) in trinity_uvd_clocks_zero()
909 if ((rps1->vclk == rps2->vclk) && in trinity_uvd_clocks_equal()
942 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); in trinity_setup_uvd_clocks()
953 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); in trinity_setup_uvd_clocks()
1457 if ((rps->vclk == pi->sys_info.uvd_clock_table_entries[i].vclk) && in trinity_get_uvd_clock_index()
1691 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); in trinity_parse_pplib_non_clock_info()
1694 rps->vclk = 0; in trinity_parse_pplib_non_clock_info()
1931 pi->sys_info.uvd_clock_table_entries[i].vclk = in trinity_parse_sys_info_table()
2017 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in trinity_dpm_print_power_state()
2042 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in trinity_dpm_debugfs_print_current_performance_level()
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| D | sumo_dpm.c | 825 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); in sumo_setup_uvd_clocks()
841 if ((new_rps->vclk == old_rps->vclk) && in sumo_set_uvd_clock_before_set_eng_clock()
859 if ((new_rps->vclk == old_rps->vclk) && in sumo_set_uvd_clock_after_set_eng_clock()
1415 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); in sumo_parse_pplib_non_clock_info()
1418 rps->vclk = 0; in sumo_parse_pplib_non_clock_info()
1802 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in sumo_dpm_print_power_state()
1825 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in sumo_dpm_debugfs_print_current_performance_level()
1833 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in sumo_dpm_debugfs_print_current_performance_level()
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| D | rv770_dpm.c | 1439 if ((new_ps->vclk == old_ps->vclk) && in rv770_set_uvd_clock_before_set_eng_clock()
1446 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv770_set_uvd_clock_before_set_eng_clock()
1456 if ((new_ps->vclk == old_ps->vclk) && in rv770_set_uvd_clock_after_set_eng_clock()
1463 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv770_set_uvd_clock_after_set_eng_clock()
2154 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); in rv7xx_parse_pplib_non_clock_info()
2157 rps->vclk = 0; in rv7xx_parse_pplib_non_clock_info()
2162 if ((rps->vclk == 0) || (rps->dclk == 0)) { in rv7xx_parse_pplib_non_clock_info()
2163 rps->vclk = RV770_DEFAULT_VCLK_FREQ; in rv7xx_parse_pplib_non_clock_info()
2440 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv770_dpm_print_power_state()
2484 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv770_dpm_debugfs_print_current_performance_level()
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| D | rv6xx_dpm.c | 1519 if ((new_ps->vclk == old_ps->vclk) && in rv6xx_set_uvd_clock_before_set_eng_clock()
1526 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv6xx_set_uvd_clock_before_set_eng_clock()
1536 if ((new_ps->vclk == old_ps->vclk) && in rv6xx_set_uvd_clock_after_set_eng_clock()
1543 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv6xx_set_uvd_clock_after_set_eng_clock()
1804 rps->vclk = RV6XX_DEFAULT_VCLK_FREQ; in rv6xx_parse_pplib_non_clock_info()
1807 rps->vclk = 0; in rv6xx_parse_pplib_non_clock_info()
2015 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv6xx_dpm_print_power_state()
2047 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv6xx_dpm_debugfs_print_current_performance_level()
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| D | radeon_uvd.c | 960 unsigned vclk, unsigned dclk, in radeon_uvd_calc_upll_dividers() argument
975 vco_min = max(max(vco_min, vclk), dclk); in radeon_uvd_calc_upll_dividers()
990 vclk_div = radeon_uvd_calc_upll_post_div(vco_freq, vclk, in radeon_uvd_calc_upll_dividers()
1002 score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div); in radeon_uvd_calc_upll_dividers()
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| D | trinity_dpm.h | 69 u32 vclk; member
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| D | radeon_asic.h | 411 int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
478 int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
535 int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
536 int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
749 int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
787 int cik_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
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| D | rv770.c | 45 int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
47 int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) in rv770_set_uvd_clocks() argument
54 return evergreen_set_uvd_clocks(rdev, vclk, dclk); in rv770_set_uvd_clocks()
61 if (!vclk || !dclk) { in rv770_set_uvd_clocks()
67 r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 50000, 160000, in rv770_set_uvd_clocks()
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| D | ni_dpm.c | 3513 if ((new_ps->vclk == old_ps->vclk) && in ni_set_uvd_clock_before_set_eng_clock()
3521 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in ni_set_uvd_clock_before_set_eng_clock()
3531 if ((new_ps->vclk == old_ps->vclk) && in ni_set_uvd_clock_after_set_eng_clock()
3539 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in ni_set_uvd_clock_after_set_eng_clock()
3902 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); in ni_parse_pplib_non_clock_info()
3905 rps->vclk = RV770_DEFAULT_VCLK_FREQ; in ni_parse_pplib_non_clock_info()
3908 rps->vclk = 0; in ni_parse_pplib_non_clock_info()
4286 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in ni_dpm_print_power_state()
4314 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in ni_dpm_debugfs_print_current_performance_level()
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| /drivers/video/fbdev/via/ |
| D | vt1636.c | 200 index = get_clk_range_index(plvds_setting_info->vclk); in viafb_vt1636_patch_skew_on_vt3324()
224 index = get_clk_range_index(plvds_setting_info->vclk); in viafb_vt1636_patch_skew_on_vt3327()
241 index = get_clk_range_index(plvds_setting_info->vclk); in viafb_vt1636_patch_skew_on_vt3364()
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| D | chip.h | 155 u32 vclk; /*panel mode clock value */ member
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| /drivers/gpu/drm/exynos/ |
| D | exynos7_drm_decon.c | 53 struct clk *vclk; member
152 clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->vclk), ideal_clk); in decon_calc_clkdiv()
723 ctx->vclk = devm_clk_get(dev, "decon0_vclk"); in decon_probe()
724 if (IS_ERR(ctx->vclk)) { in decon_probe()
726 ret = PTR_ERR(ctx->vclk); in decon_probe()
791 clk_disable_unprepare(ctx->vclk); in exynos7_decon_suspend()
822 ret = clk_prepare_enable(ctx->vclk); in exynos7_decon_resume()
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| /drivers/video/fbdev/aty/ |
| D | aty128fb.c | 432 u32 vclk; member
1376 u32 vclk; /* in .01 MHz */ in aty128_var_to_pll() local
1380 vclk = 100000000 / period_in_ps; /* convert units to 10 kHz */ in aty128_var_to_pll()
1383 if (vclk > c.ppll_max) in aty128_var_to_pll()
1384 vclk = c.ppll_max; in aty128_var_to_pll()
1385 if (vclk * 12 < c.ppll_min) in aty128_var_to_pll()
1386 vclk = c.ppll_min/12; in aty128_var_to_pll()
1390 output_freq = post_dividers[i] * vclk; in aty128_var_to_pll()
1405 pll->vclk = vclk; in aty128_var_to_pll()
1409 pll->feedback_divider, vclk, output_freq, in aty128_var_to_pll()
[all …]
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| /drivers/gpu/drm/amd/powerplay/hwmgr/ |
| D | cz_hwmgr.c | 140 if (clock <= ptable->entries[i].vclk) in cz_get_uvd_level()
148 if (clock >= ptable->entries[i].vclk) in cz_get_uvd_level()
528 (i < uvd_table->count) ? uvd_table->entries[i].vclk : 0; in cz_tf_upload_pptable_to_smu()
614 clock = table->entries[level].vclk; in cz_tf_init_uvd_limit()
616 clock = table->entries[table->count - 1].vclk; in cz_tf_init_uvd_limit()
1118 cz_hwmgr->video_start = (hwmgr->uvd_arbiter.vclk != 0 || hwmgr->uvd_arbiter.dclk != 0 || in cz_apply_state_adjust_rules()
1462 ptable->entries[ptable->count - 1].vclk; in cz_dpm_update_uvd_dpm()
1632 cz_ps->uvd_clocks.vclk = ps->uvd_clocks.VCLK; in cz_dpm_get_pp_table_entry()
1926 uint32_t sclk, vclk, dclk, ecclk, tmp, activity_percent; in cz_read_sensor() local
1960 vclk = uvd_table->entries[uvd_index].vclk; in cz_read_sensor()
[all …]
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| D | hwmgr_ppt.h | 60 uint32_t vclk; /* UVD V-clock */ member
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| D | rv_hwmgr.h | 97 uint32_t vclk; member
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| D | smu7_hwmgr.h | 73 uint32_t vclk; member
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| D | cz_hwmgr.h | 118 uint32_t vclk; member
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| /drivers/gpu/drm/nouveau/dispnv04/ |
| D | arb.c | 253 nouveau_calc_arb(struct drm_device *dev, int vclk, int bpp, int *burst, int *lwm) in nouveau_calc_arb() argument
258 nv04_update_arb(dev, vclk, bpp, burst, lwm); in nouveau_calc_arb()
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| /drivers/gpu/drm/amd/powerplay/inc/ |
| D | eventmgr.h | 92 uint32_t vclk; member
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| D | power_state.h | 176 unsigned long vclk; member
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| D | hwmgr.h | 127 uint32_t vclk; member
193 uint32_t vclk; member
233 uint32_t vclk; member
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| /drivers/gpu/drm/amd/amdgpu/ |
| D | kv_dpm.c | 921 pi->uvd_level[i].VclkFrequency = cpu_to_be32(table->entries[i].vclk); in kv_populate_uvd_table()
926 (u8)kv_get_clk_bypass(adev, table->entries[i].vclk); in kv_populate_uvd_table()
931 table->entries[i].vclk, false, ÷rs); in kv_populate_uvd_table()
2274 pi->video_start = new_rps->dclk || new_rps->vclk || in kv_apply_state_adjust_rules()
2650 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); in kv_parse_pplib_non_clock_info()
2653 rps->vclk = 0; in kv_parse_pplib_non_clock_info()
2884 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in kv_dpm_print_power_state()
3257 *equal = ((cps->vclk == rps->vclk) && (cps->dclk == rps->dclk)); in kv_check_state_equal()
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| D | amdgpu_dpm.h | 62 u32 vclk; member
150 u32 vclk; member
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