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Searched refs:PORT (Results 1 – 25 of 28) sorted by relevance

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/arch/mips/boot/compressed/
Duart-16550.c12 #define PORT(offset) (CKSEG1ADDR(UART_BASE) + (offset)) macro
17 #define PORT(offset) (CKSEG1ADDR(AR7_REGS_UART0) + (4 * offset)) macro
22 #define PORT(offset) (CKSEG1ADDR(JZ4740_UART0_BASE_ADDR) + (4 * offset)) macro
27 #define PORT(offset) (CKSEG1ADDR(UART0_BASE) + (4 * offset)) macro
33 #define PORT(offset) (CKSEG1ADDR(UART0_BASE) + (4 * offset)) macro
41 #ifndef PORT
47 return *((volatile IOTYPE *)PORT(offset)) & 0xFF; in serial_in()
52 *((volatile IOTYPE *)PORT(offset)) = value & 0xFF; in serial_out()
/arch/mips/kernel/
D8250-platform.c11 #define PORT(base, int) \ macro
22 PORT(0x3F8, 4),
23 PORT(0x2F8, 3),
24 PORT(0x3E8, 4),
25 PORT(0x2E8, 3),
/arch/blackfin/mach-bf527/
DKconfig17 Select PORT used for SPORT0. See Hardware Reference Manual
20 bool "PORT F"
22 PORT F
25 bool "PORT G"
27 PORT G
38 bool "PORT PG10"
40 PORT PG10
43 bool "PORT PG14"
45 PORT PG14
52 Select PORT used for UART1. See Hardware Reference Manual
[all …]
/arch/mips/alchemy/common/
Dplatform.c51 #define PORT(_base, _irq) \ macro
65 PORT(AU1000_UART0_PHYS_ADDR, AU1000_UART0_INT),
66 PORT(AU1000_UART1_PHYS_ADDR, AU1000_UART1_INT),
67 PORT(AU1000_UART2_PHYS_ADDR, AU1000_UART2_INT),
68 PORT(AU1000_UART3_PHYS_ADDR, AU1000_UART3_INT),
71 PORT(AU1000_UART0_PHYS_ADDR, AU1500_UART0_INT),
72 PORT(AU1000_UART3_PHYS_ADDR, AU1500_UART3_INT),
75 PORT(AU1000_UART0_PHYS_ADDR, AU1100_UART0_INT),
76 PORT(AU1000_UART1_PHYS_ADDR, AU1100_UART1_INT),
77 PORT(AU1000_UART3_PHYS_ADDR, AU1100_UART3_INT),
[all …]
/arch/mips/loongson64/common/
Dearly_printk.c16 #define PORT(base, offset) (u8 *)(base + offset) macro
20 return readb(PORT(base, offset)); in serial_in()
25 writeb(value, PORT(base, offset)); in serial_out()
Dserial.c22 #define PORT(int, clk) \ macro
43 [MACH_LEMOTE_FL2E] = {PORT(4, 1843200), {} },
44 [MACH_LEMOTE_FL2F] = {PORT(3, 1843200), {} },
49 [MACH_LEMOTE_LL2F] = {PORT(3, 1843200), {} },
/arch/mips/mti-sead3/
Dsead3-console.c15 #define PORT(base_addr, offset) ((unsigned int __iomem *)(base_addr+(offset)*4)) macro
21 return __raw_readl(PORT(base_addr, offset)) & 0xff; in serial_in()
26 __raw_writel(value, PORT(base_addr, offset)); in serial_out()
/arch/mips/sni/
Dpcit.c22 #define PORT(_base,_irq) \ macro
32 PORT(0x3f8, 0),
33 PORT(0x2f8, 3),
46 PORT(0x3f8, 0),
47 PORT(0x2f8, 3),
48 PORT(0x3e8, 4),
49 PORT(0x2e8, 3),
Da20r.c20 #define PORT(_base,_irq) \ macro
30 PORT(0x3f8, 4),
31 PORT(0x2f8, 3),
Dpcimt.c70 #define PORT(_base,_irq) \ macro
80 PORT(0x3f8, 4),
81 PORT(0x2f8, 3),
/arch/mips/netlogic/xlr/
Dplatform.c60 #define PORT(_irq) \ macro
74 PORT(PIC_UART_0_IRQ),
75 PORT(PIC_UART_1_IRQ),
/arch/mips/ar7/
Dprom.c251 #define PORT(offset) (KSEG1ADDR(AR7_REGS_UART0 + (offset * 4))) macro
254 return readl((void *)PORT(offset)); in serial_in()
259 writel(value, (void *)PORT(offset)); in serial_out()
/arch/blackfin/mach-bf518/
DKconfig95 menu "PORT F"
111 menu "PORT G"
131 menu "PORT H"
/arch/avr32/mach-at32ap/include/mach/
Dat32ap700x.h143 #define ATMEL_LCDC(PORT, PIN) (ATMEL_LCDC_##PORT##_##PIN) argument
/arch/arm/boot/dts/
Domap3-cm-t3x.dtsi41 /* HS USB Host PHY on PORT 1 */
47 /* HS USB Host PHY on PORT 2 */
Domap5-board-common.dtsi42 /* HS USB Host PHY on PORT 2 */
51 /* HS USB Host PHY on PORT 3 */
Domap3-igep0020-common.dtsi56 /* HS USB Host PHY on PORT 1 */
Domap4-duovero.dtsi38 /* HS USB Host PHY on PORT 1 */
Domap5-cm-t54.dts61 /* HS USB Host PHY on PORT 2 */
67 /* HS USB Host PHY on PORT 3 */
Domap4-var-som-om44.dtsi36 /* HS USB Host PHY on PORT 1 */
Domap3-overo-base.dtsi43 /* HS USB Host PHY on PORT 2 */
Domap3-beagle-xm.dts87 /* HS USB Host PHY on PORT 2 */
Domap3-tao3530.dtsi44 /* HS USB Host PHY on PORT 2 */
Domap3-beagle.dts62 /* HS USB Host PHY on PORT 2 */
/arch/blackfin/kernel/
Ddebug-mmrs.c362 _buf = REGS_STR_PFX_C(buf, PORT, num); in bfin_debug_mmrs_port()
392 #define PORT(base, num) bfin_debug_mmrs_port(parent, base, num) macro
1780 PORT(PORTFIO, 'F'); in bfin_debug_mmrs_init()
1783 PORT(PORTGIO, 'G'); in bfin_debug_mmrs_init()
1786 PORT(PORTHIO, 'H'); in bfin_debug_mmrs_init()
1873 PORT(base, num); in bfin_debug_mmrs_init()

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