| /arch/mips/cavium-octeon/executive/ |
| D | cvmx-helper-errata.c | 51 int lane; in __cvmx_helper_errata_qlm_disable_2nd_order_cdr() local
54 for (lane = 0; lane < 4; lane++) { in __cvmx_helper_errata_qlm_disable_2nd_order_cdr()
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| /arch/x86/crypto/sha-mb/ |
| D | sha1_mb_mgr_submit_avx2.S | 89 lane = %rbp define
118 mov unused_lanes, lane
119 and $0xF, lane
121 imul $_LANE_DATA_size, lane, lane_data
129 or lane, len
131 movl DWORD_len, _lens(state , lane, 4)
136 vmovd %xmm0, _args_digest(state, lane, 4)
137 vpextrd $1, %xmm0, _args_digest+1*32(state , lane, 4)
138 vpextrd $2, %xmm0, _args_digest+2*32(state , lane, 4)
139 vpextrd $3, %xmm0, _args_digest+3*32(state , lane, 4)
[all …]
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| D | sha1_mb_mgr_flush_avx2.S | 132 # find a lane with a non-null job
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| /arch/arm/mach-mv78xx0/ |
| D | pcie.c | 21 #define MV78XX0_MBUS_PCIE_MEM_TARGET(port, lane) ((port) ? 8 : 4) argument
22 #define MV78XX0_MBUS_PCIE_MEM_ATTR(port, lane) (0xf8 & ~(0x10 << (lane))) argument
23 #define MV78XX0_MBUS_PCIE_IO_TARGET(port, lane) ((port) ? 8 : 4) argument
24 #define MV78XX0_MBUS_PCIE_IO_ATTR(port, lane) (0xf0 & ~(0x10 << (lane))) argument
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| /arch/arm/boot/dts/ |
| D | armada-xp-mv78460.dtsi | 165 marvell,pcie-lane = <0>;
182 marvell,pcie-lane = <1>;
199 marvell,pcie-lane = <2>;
216 marvell,pcie-lane = <3>;
233 marvell,pcie-lane = <0>;
250 marvell,pcie-lane = <1>;
267 marvell,pcie-lane = <2>;
284 marvell,pcie-lane = <3>;
301 marvell,pcie-lane = <0>;
318 marvell,pcie-lane = <0>;
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| D | armada-xp-mv78260.dtsi | 144 marvell,pcie-lane = <0>;
161 marvell,pcie-lane = <1>;
178 marvell,pcie-lane = <2>;
195 marvell,pcie-lane = <3>;
212 marvell,pcie-lane = <0>;
229 marvell,pcie-lane = <1>;
246 marvell,pcie-lane = <2>;
263 marvell,pcie-lane = <3>;
280 marvell,pcie-lane = <0>;
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| D | armada-xp-mv78230.dtsi | 129 marvell,pcie-lane = <0>;
146 marvell,pcie-lane = <1>;
163 marvell,pcie-lane = <2>;
180 marvell,pcie-lane = <3>;
197 marvell,pcie-lane = <0>;
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| D | armada-385.dtsi | 121 marvell,pcie-lane = <0>;
139 marvell,pcie-lane = <0>;
157 marvell,pcie-lane = <0>;
178 marvell,pcie-lane = <0>;
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| D | kirkwood-98dx4122.dtsi | 30 marvell,pcie-lane = <0>;
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| D | kirkwood-6282.dtsi | 34 marvell,pcie-lane = <0>;
51 marvell,pcie-lane = <0>;
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| D | armada-380.dtsi | 110 marvell,pcie-lane = <0>;
128 marvell,pcie-lane = <0>;
146 marvell,pcie-lane = <0>;
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| D | omap3-n950.dts | 51 lane-polarities = <1 1 1>;
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| D | omap3-n9.dts | 51 lane-polarities = <1 1 1>;
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| D | kirkwood-6192.dtsi | 30 marvell,pcie-lane = <0>;
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| D | kirkwood-6281.dtsi | 30 marvell,pcie-lane = <0>;
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| D | armada-39x.dtsi | 442 marvell,pcie-lane = <0>;
460 marvell,pcie-lane = <0>;
478 marvell,pcie-lane = <0>;
499 marvell,pcie-lane = <0>;
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| D | lpc4350-hitex-eval.dts | 340 mpmc,byte-lane-low;
377 mpmc,byte-lane-low;
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| D | armada-370.dtsi | 104 marvell,pcie-lane = <0>;
121 marvell,pcie-lane = <0>;
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| D | armada-375.dtsi | 614 marvell,pcie-lane = <0>;
631 marvell,pcie-lane = <1>;
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| D | exynos5250-smdk5250.dts | 87 samsung,lane-count = <4>;
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| D | exynos5420-smdk5420.dts | 100 samsung,lane-count = <4>;
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| D | exynos5420-peach-pit.dts | 155 samsung,lane-count = <2>;
623 lane-count = <2>;
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| D | lpc4357-ea4357-devkit.dts | 493 mpmc,byte-lane-low;
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| D | exynos5250-arndale.dts | 131 samsung,lane-count = <4>;
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| /arch/sh/drivers/pci/ |
| D | pcie-sh7786.c | 182 unsigned int lane, unsigned int data) in phy_write_reg() argument
186 phyaddr = (1 << BITS_CMD) + ((lane & 0xf) << BITS_LANE) + in phy_write_reg()
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