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Searched refs:mcr (Results 1 – 25 of 96) sorted by relevance

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/arch/arm/mm/
D	proc-arm940.S	`43 mcr p15, 0, r0, c1, c0, 0 @ disable caches 54 mcr p15, 0, ip, c7, c5, 0 @ flush I cache 55 mcr p15, 0, ip, c7, c6, 0 @ flush D cache 56 mcr p15, 0, ip, c7, c10, 4 @ drain WB 60 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 70 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 80 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 112 mcr p15, 0, ip, c7, c6, 0 @ flush D cache 116 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index 166 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index [all …]`
D	proc-mohawk.S	57 mcr p15, 0, r0, c1, c0, 0 @ disable caches 75 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 76 mcr p15, 0, ip, c7, c10, 4 @ drain WB 77 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 81 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 94 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 95 mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt 105 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 127 mcr p15, 0, ip, c7, c14, 0 @ clean & invalidate all D cache 151 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry [all …]
D	proc-fa526.S	44 mcr p15, 0, r0, c1, c0, 0 @ disable caches 63 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 64 mcr p15, 0, ip, c7, c10, 4 @ drain WB 66 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 72 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 88 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 92 mcr p15, 0, r0, c7, c10, 4 @ drain WB 109 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 111 mcr p15, 0, ip, c7, c14, 0 @ clean and invalidate whole D cache 113 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache [all …]
D	proc-arm946.S	`50 mcr p15, 0, r0, c1, c0, 0 @ disable caches 61 mcr p15, 0, ip, c7, c5, 0 @ flush I cache 62 mcr p15, 0, ip, c7, c6, 0 @ flush D cache 63 mcr p15, 0, ip, c7, c10, 4 @ drain WB 67 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 77 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 87 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 107 mcr p15, 0, ip, c7, c6, 0 @ flush D cache 111 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index 141 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry [all …]`
D	proc-arm1020.S	`83 mcr p15, 0, r0, c1, c0, 0 @ disable caches 99 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 100 mcr p15, 0, ip, c7, c10, 4 @ drain WB 102 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 107 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 117 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 132 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 155 mcr p15, 0, ip, c7, c10, 4 @ drain WB 158 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 159 mcr p15, 0, ip, c7, c10, 4 @ drain WB [all …]`
D	proc-arm926.S	67 mcr p15, 0, r0, c1, c0, 0 @ disable caches 83 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 84 mcr p15, 0, ip, c7, c10, 4 @ drain WB 86 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 91 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 105 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer 110 mcr p15, 0, r2, c1, c0, 0 @ Disable I cache 111 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 112 mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable 123 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache [all …]
D	proc-arm925.S	98 mcr p15, 0, r0, c1, c0, 0 @ disable caches 123 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 124 mcr p15, 0, ip, c7, c10, 4 @ drain WB 126 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 131 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 143 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer 145 mcr p15, 0, r2, c1, c0, 0 @ Disable I cache 146 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 147 mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable 157 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache [all …]
D	proc-arm920.S	75 mcr p15, 0, r0, c1, c0, 0 @ disable caches 91 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 92 mcr p15, 0, ip, c7, c10, 4 @ drain WB 94 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 99 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 109 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 122 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 146 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 172 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 207 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry [all …]
D	cache-v6.S	43 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 44 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 45 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 46 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 52 mcr p15, 0, r0, c7, c5, 0 @ invalidate I-cache 67 mcr p15, 0, r0, c7, c14, 0 @ D cache clean+invalidate 69 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate 74 mcr p15, 0, r0, c7, c15, 0 @ Cache clean+invalidate 137 USER( mcr p15, 0, r0, c7, c10, 1 ) @ clean D line 144 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer [all …]
D	proc-sa1100.S	44 mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching 45 mcr p15, 0, r0, c9, c0, 5 @ Allow read-buffer operations from userland 56 mcr p15, 0, ip, c15, c2, 2 @ Disable clock switching 60 mcr p15, 0, r0, c1, c0, 0 @ disable caches 76 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 77 mcr p15, 0, ip, c7, c10, 4 @ drain WB 79 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 84 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 111 mcr p15, 0, r0, c15, c2, 2 @ disable clock switching 113 mcr p15, 0, r0, c15, c8, 2 @ wait for interrupt [all …]
D	proc-v6.S	`45 mcr p15, 0, r0, c1, c0, 0 @ disable caches 62 mcr p15, 0, r1, c1, c0, 0 @ disable MMU 64 mcr p15, 0, r1, c7, c5, 4 @ ISB 78 mcr p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode 79 mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt 83 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 105 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB 106 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer 107 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 114 mcr p15, 0, r1, c13, c0, 1 @ set context ID [all …]`
D	proc-arm922.S	77 mcr p15, 0, r0, c1, c0, 0 @ disable caches 93 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 94 mcr p15, 0, ip, c7, c10, 4 @ drain WB 96 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 101 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 111 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 124 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 148 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 174 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 209 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry [all …]
D	proc-arm1020e.S	83 mcr p15, 0, r0, c1, c0, 0 @ disable caches 99 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 100 mcr p15, 0, ip, c7, c10, 4 @ drain WB 102 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 107 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 117 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 132 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 155 mcr p15, 0, ip, c7, c10, 4 @ drain WB 158 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 188 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry [all …]
D	proc-feroceon.S	`81 mcr p15, 1, r0, c15, c9, 0 @ clean L2 82 mcr p15, 0, r0, c7, c10, 4 @ drain WB 88 mcr p15, 0, r0, c1, c0, 0 @ disable caches 104 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 105 mcr p15, 0, ip, c7, c10, 4 @ drain WB 107 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 112 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 125 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer 126 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 136 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache [all …]`
D	proc-sa110.S	40 mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching 48 mcr p15, 0, r0, c15, c2, 2 @ Disable clock switching 52 mcr p15, 0, r0, c1, c0, 0 @ disable caches 68 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 69 mcr p15, 0, ip, c7, c10, 4 @ drain WB 71 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 76 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 95 mcr p15, 0, ip, c15, c2, 2 @ disable clock switching 101 mcr p15, 0, r0, c15, c8, 2 @ Wait for interrupt, cache aligned 105 mcr p15, 0, r0, c15, c1, 2 @ enable clock switching [all …]
D	proc-xscale.S	94 1: mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 96 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 98 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 100 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 120 mcr p15, 0, r1, c1, c0, 1 130 mcr p15, 0, r0, c1, c0, 0 @ disable caches 149 mcr p15, 0, r1, c10, c4, 1 @ unlock I-TLB 150 mcr p15, 0, r1, c8, c5, 0 @ invalidate I-TLB 156 mcr p15, 0, r1, c1, c0, 0 @ ctrl register 158 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches & BTB [all …]
D	proc-arm1022.S	74 mcr p15, 0, r0, c1, c0, 0 @ disable caches 90 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 91 mcr p15, 0, ip, c7, c10, 4 @ drain WB 93 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 98 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 108 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 123 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 148 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 178 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 218 mcr p15, 0, r0, c7, c10, 1 @ clean D entry [all …]
D	proc-arm1026.S	74 mcr p15, 0, r0, c1, c0, 0 @ disable caches 90 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 91 mcr p15, 0, ip, c7, c10, 4 @ drain WB 93 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 98 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 108 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 123 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 173 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 212 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 215 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry [all …]
D	proc-xsc3.S	71 1: mcr p15, 0, \rd, c7, c14, 2 @ clean/invalidate L1 D line 95 mcr p15, 0, r0, c1, c0, 0 @ disable caches 115 mcr p15, 0, r1, c1, c0, 0 @ ctrl register 116 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB 118 mcr p15, 0, r1, c1, c0, 0 @ ctrl register 121 mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs 140 mcr p14, 0, r0, c7, c0, 0 @ go to idle 152 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 200 mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line 227 1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line [all …]
D	proc-arm740.S	`44 mcr p15, 0, r0, c1, c0, 0 @ disable caches 55 mcr p15, 0, ip, c7, c0, 0 @ invalidate cache 58 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 66 mcr p15, 0, r0, c7, c0, 0 @ invalidate caches 68 mcr p15, 0, r0, c6, c3 @ disable area 3~7 69 mcr p15, 0, r0, c6, c4 70 mcr p15, 0, r0, c6, c5 71 mcr p15, 0, r0, c6, c6 72 mcr p15, 0, r0, c6, c7 75 mcr p15, 0, r0, c6, c0 @ set area 0, default [all …]`
D	cache-fa.S	48 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 69 mcr p15, 0, ip, c7, c14, 0 @ clean/invalidate D cache 95 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 130 1: mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 131 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 136 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB 137 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 138 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush 152 1: mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line 157 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache [all …]
D	tlb-v6.S	40 mcr p15, 0, ip, c7, c10, 4 @ drain write buffer 49 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA (was 1) 53 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA (was 1) 58 mcr p15, 0, ip, c7, c10, 4 @ data synchronization barrier 71 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer 78 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA 79 mcr p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA 81 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA 86 mcr p15, 0, r2, c7, c10, 4 @ data synchronization barrier 87 mcr p15, 0, r2, c7, c5, 4 @ prefetch flush (isb)
D	tlb-fa.S	`43 mcr p15, 0, r3, c7, c10, 4 @ drain WB 46 1: mcr p15, 0, r0, c8, c7, 1 @ invalidate UTLB entry 50 mcr p15, 0, r3, c7, c10, 4 @ data write barrier 56 mcr p15, 0, r3, c7, c10, 4 @ drain WB 59 1: mcr p15, 0, r0, c8, c7, 1 @ invalidate UTLB entry 63 mcr p15, 0, r3, c7, c10, 4 @ data write barrier 64 mcr p15, 0, r3, c7, c5, 4 @ prefetch flush (isb)`
/arch/sh/drivers/pci/
D	fixups-landisk.c	`43 unsigned long bcr1, mcr; in pci_fixup_pcic() local 49 mcr = __raw_readl(SH7751_MCR); in pci_fixup_pcic() 50 mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF; in pci_fixup_pcic() 51 pci_write_reg(chan, mcr, SH4_PCIMCR); in pci_fixup_pcic()`
/arch/x86/platform/intel/
D	iosf_mbi.c	43 static int iosf_mbi_pci_read_mdr(u32 mcrx, u32 mcr, u32 *mdr) in iosf_mbi_pci_read_mdr() argument 57 result = pci_write_config_dword(mbi_pdev, MBI_MCR_OFFSET, mcr); in iosf_mbi_pci_read_mdr() 72 static int iosf_mbi_pci_write_mdr(u32 mcrx, u32 mcr, u32 mdr) in iosf_mbi_pci_write_mdr() argument 90 result = pci_write_config_dword(mbi_pdev, MBI_MCR_OFFSET, mcr); in iosf_mbi_pci_write_mdr() 103 u32 mcr, mcrx; in iosf_mbi_read() local 113 mcr = iosf_mbi_form_mcr(opcode, port, offset & MBI_MASK_LO); in iosf_mbi_read() 117 ret = iosf_mbi_pci_read_mdr(mcrx, mcr, mdr); in iosf_mbi_read() 126 u32 mcr, mcrx; in iosf_mbi_write() local 136 mcr = iosf_mbi_form_mcr(opcode, port, offset & MBI_MASK_LO); in iosf_mbi_write() 140 ret = iosf_mbi_pci_write_mdr(mcrx, mcr, mdr); in iosf_mbi_write() [all …]

12 3 4

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