Searched refs:vulp (Results 1 – 12 of 12) sorted by relevance
191 t2_cfg = *(vulp)T2_HAE_3 & ~0xc0000000UL; in conf_read()192 *(vulp)T2_HAE_3 = 0x40000000UL | t2_cfg; in conf_read()226 *(vulp)T2_HAE_3 = t2_cfg; in conf_read()243 t2_cfg = *(vulp)T2_HAE_3 & ~0xc0000000UL; in conf_write()244 *(vulp)T2_HAE_3 = t2_cfg | 0x40000000UL; in conf_write()277 *(vulp)T2_HAE_3 = t2_cfg; in conf_write()333 *(vulp)T2_WBASE1 = temp | 0x80000UL; /* OR in ENABLE bit */ in t2_direct_map_window1()335 *(vulp)T2_WMASK1 = temp; in t2_direct_map_window1()336 *(vulp)T2_TBASE1 = 0; in t2_direct_map_window1()340 __func__, *(vulp)T2_WBASE1, *(vulp)T2_WMASK1, *(vulp)T2_TBASE1); in t2_direct_map_window1()[all …]
26 *(vulp)PYXIS_INT_MASK = mask; in pyxis_update_irq_hw()28 *(vulp)PYXIS_INT_MASK; in pyxis_update_irq_hw()50 *(vulp)PYXIS_INT_MASK = mask; in pyxis_mask_and_ack_irq()53 *(vulp)PYXIS_INT_REQ = bit; in pyxis_mask_and_ack_irq()56 *(vulp)PYXIS_INT_MASK; in pyxis_mask_and_ack_irq()73 pld = *(vulp)PYXIS_INT_REQ; in pyxis_device_interrupt()95 *(vulp)PYXIS_INT_MASK = 0; /* disable all */ in init_pyxis_irqs()96 *(vulp)PYXIS_INT_REQ = -1; /* flush all */ in init_pyxis_irqs()
117 *(vulp)LCA_IOC_CONF = 0; in mk_conf_addr()121 *(vulp)LCA_IOC_CONF = 1; in mk_conf_addr()137 stat0 = *(vulp)LCA_IOC_STAT0; in conf_read()138 *(vulp)LCA_IOC_STAT0 = stat0; in conf_read()145 stat0 = *(vulp)LCA_IOC_STAT0; in conf_read()154 *(vulp)LCA_IOC_STAT0 = stat0; in conf_read()174 stat0 = *(vulp)LCA_IOC_STAT0; in conf_write()175 *(vulp)LCA_IOC_STAT0 = stat0; in conf_write()182 stat0 = *(vulp)LCA_IOC_STAT0; in conf_write()191 *(vulp)LCA_IOC_STAT0 = stat0; in conf_write()[all …]
39 *(vulp)PYXIS_INT_HILO = 0x000000c0UL; mb(); in ruffian_init_irq()40 *(vulp)PYXIS_INT_CNFG = 0x00002064UL; mb(); /* all clear */ in ruffian_init_irq()188 bank = *(vulp)bank_addr; in ruffian_get_bank_size()
298 *(vulp)T2_AIR = 0x40; in lynx_update_irq_hw()300 *(vulp)T2_AIR; /* re-read to force write */ in lynx_update_irq_hw()302 *(vulp)T2_DIR = mask; in lynx_update_irq_hw()310 *(vulp)T2_VAR = (u_long) bit; in lynx_ack_irq_hw()
69 *(vulp)PYXIS_INT_HILO = 0x000000B2UL; mb(); /* ISA/NMI HI */ in miata_init_irq()70 *(vulp)PYXIS_RT_COUNT = 0UL; mb(); /* clear count */ in miata_init_irq()
12 #define vulp volatile unsigned long * macro
795 pyxis_cc = *(vulp)PYXIS_RT_COUNT; in pyxis_init_arch()796 do { } while(*(vulp)PYXIS_RT_COUNT - pyxis_cc < 4096); in pyxis_init_arch()
1404 sc_ctl = *(vulp) phys_to_virt (0xfffff000a8UL); in determine_cpu_caches()1437 cbox_config = *(vulp) phys_to_virt (0xfffff00008UL); in determine_cpu_caches()
220 #define vulp volatile unsigned long __force * macro343 #undef vulp
342 #define vulp volatile unsigned long __force * macro466 #undef vulp
375 #define vulp volatile unsigned long __force * macro499 #undef vulp