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Searched refs:BIT4 (Results 1 – 25 of 29) sorted by relevance

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/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/
Dpwrseq.h121 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, BIT4 \
183 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, BIT4 \
301 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \
397 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \
408 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3|BIT2), 0 \
426 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3), 0 \
438 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT5|BIT4), (BIT5|BIT4) \
497 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3) \
501 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3 \
504 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4 \
[all …]
/drivers/staging/rtl8192e/rtl8192e/
Dr8192E_hw.h111 #define EPROM_CMD_9356SEL BIT4
215 #define SCR_SKByA2 BIT4
234 #define IMR_BKDOK BIT4
245 #define TPPoll_BQ BIT4
285 #define AcmHw_BeqStatus BIT4
375 #define RRSR_6M BIT4
Drtl_pci.c37 tmp |= BIT4; in _rtl92e_parse_pci_configuration()
Dr8192E_phy.c1409 rtl92e_set_bb_reg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x0); in rtl92e_set_rf_off()
1470 BIT4, 0x1); in _rtl92e_set_rf_power_state()
/drivers/scsi/
Ddc395x.h71 #define BIT4 0x00000010 macro
132 #define PARITY_ERROR BIT4
139 #define ENABLE_TIMER BIT4
177 #define WIDE_NEGO_STATE BIT4
633 #define NO_SEEK BIT4
/drivers/video/fbdev/via/
Ddvi.c75 viafb_write_reg_mask(SR1E, VIASR, 0xF0, BIT4 + in viafb_tmds_trasmitter_identify()
340 viafb_write_reg_mask(SR2A, VIASR, 0, BIT4); in dvi_patch_skew_dvp0()
361 viafb_write_reg_mask(SR2A, VIASR, 0x10, BIT4); in dvi_patch_skew_dvp0()
Dhw.c962 viafb_write_reg_mask(CR35, VIACR, 0x10, BIT4); in load_fix_bit_crtc_reg()
1728 viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5); in set_display_channel()
1732 viafb_write_reg_mask(CRD2, VIACR, 0x10, BIT4 + BIT5); in set_display_channel()
1735 viafb_write_reg_mask(CRD2, VIACR, 0x30, BIT4 + BIT5); in set_display_channel()
1740 viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5); in set_display_channel()
1743 viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT4 + BIT5); in set_display_channel()
2076 BIT4); in viafb_set_dpa_gfx()
Dshare.h32 #define BIT4 0x10 macro
Dlcd.c857 bdual = BIT4; in fill_lcd_format()
861 viafb_write_reg_mask(CR88, VIACR, (bdithering | bdual), BIT4 + BIT0); in fill_lcd_format()
Dviafbdev.c1131 (viafb_read_reg(VIASR, SR2A) & BIT4) >> 3 | in viafb_dvp0_proc_show()
1176 reg_val << 3, BIT4); in viafb_dvp0_proc_write()
/drivers/net/wireless/realtek/rtlwifi/btcoexist/
Dhalbt_precomp.h52 #define BIT4 0x00000010 macro
Dhalbtcoutsrc.h105 #define ALGO_TRACE_FW BIT4
117 #define WIFI_P2P_GC_CONNECTED BIT4
Dhalbtc8723b2ant.h36 #define BT_INFO_8723B_2ANT_B_SCO_BUSY BIT4
Dhalbtc8821a2ant.h33 #define BT_INFO_8821A_2ANT_B_SCO_BUSY BIT4
Dhalbtc8723b1ant.h33 #define BT_INFO_8723B_1ANT_B_SCO_BUSY BIT4
Dhalbtc8192e2ant.h33 #define BT_INFO_8192E_2ANT_B_SCO_BUSY BIT4
Dhalbtc8821a1ant.h35 #define BT_INFO_8821A_1ANT_B_SCO_BUSY BIT4
Dhalbtc8723b1ant.c884 if ((byte1 & BIT4) && !(byte1 & BIT5)) { in halbtc8723b1ant_set_fw_ps_tdma()
887 real_byte1 &= ~BIT4; in halbtc8723b1ant_set_fw_ps_tdma()
2987 if (coex_sta->bt_info_ext & BIT4) { in ex_halbtc8723b1ant_bt_info_notify()
Dhalbtc8192e2ant.c3271 u8tmp |= BIT4; in halbtc8192e2ant_init_hwconfig()
3710 if ((coex_sta->bt_info_ext & BIT4)) { in ex_halbtc8192e2ant_bt_info_notify()
/drivers/staging/rtl8192e/
Drtl819x_Qos.h22 #define BIT4 0x00000010 macro
/drivers/tty/
Dsynclink.c492 #define RECEIVE_DATA BIT4
509 #define RXSTATUS_RXBOUND BIT4
548 #define TXSTATUS_EOF_SENT BIT4
549 #define TXSTATUS_EOM_SENT BIT4
569 #define MISCSTATUS_CTS BIT4
594 #define SICR_CTS_INACTIVE BIT4
595 #define SICR_CTS (BIT5|BIT4)
629 #define TXSTATUS_EOF BIT4
4727 RegValue |= BIT4; in usc_set_sdlc_mode()
4999 RegValue |= BIT4; /* enable BRG1 */ in usc_set_sdlc_mode()
[all …]
Dsynclinkmp.c423 #define SYNCD BIT4
424 #define FLGD BIT4
439 #define FRME BIT4
440 #define RBIT BIT4
2598 if (timerstatus0 & (BIT5 | BIT4)) in synclinkmp_interrupt()
2602 if (timerstatus1 & (BIT5 | BIT4)) in synclinkmp_interrupt()
4410 case 7: RegValue |= BIT4 + BIT2; break; in async_mode()
4412 case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break; in async_mode()
4543 RegValue |= BIT4; in hdlc_mode()
4545 RegValue |= BIT4; in hdlc_mode()
[all …]
Dsynclink_gt.c385 #define MASK_OVERRUN BIT4
423 #define IRQ_RI BIT4
2220 if (status & (BIT5 + BIT4)) { in isr_rdma()
2245 if (status & (BIT5 + BIT4 + BIT3)) { in isr_tdma()
4158 case 6: val |= BIT4; break; in async_mode()
4160 case 8: val |= BIT5 + BIT4; break; in async_mode()
4198 case 6: val |= BIT4; break; in async_mode()
4200 case 8: val |= BIT5 + BIT4; break; in async_mode()
4324 case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break; in sync_mode()
4325 case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break; in sync_mode()
[all …]
/drivers/char/pcmcia/
Dsynclink_cs.c681 #define CMD_START_TIMER BIT4
3027 val = read_reg(info, CHA + CCR2) | (BIT4 | BIT5); in loopback_enable()
3114 val |= BIT4; in hdlc_mode()
3117 val |= BIT4 | BIT2; in hdlc_mode()
3120 val |= BIT4 | BIT3; in hdlc_mode()
3156 val |= BIT4; in hdlc_mode()
3523 val |= BIT4; in async_mode()
3680 if (!(status & BIT7) || (status & BIT4)) in rx_get_frame()
/drivers/net/wireless/realtek/rtlwifi/rtl8192de/
Dreg.h388 #define RRSR_6M BIT4

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