| /drivers/clk/ |
| D | clk-nspire.c | 17 #define MHZ (1000 * 1000) macro
48 clk->base_clock = 48 * MHZ; in nspire_clkinfo_cx()
50 clk->base_clock = 6 * EXTRACT(val, CX_BASE) * MHZ; in nspire_clkinfo_cx()
59 clk->base_clock = 27 * MHZ; in nspire_clkinfo_classic()
61 clk->base_clock = (300 - 6 * EXTRACT(val, CLASSIC_BASE)) * MHZ; in nspire_clkinfo_classic()
136 info.base_clock / MHZ, in nspire_clk_setup()
137 info.base_clock / info.base_cpu_ratio / MHZ, in nspire_clk_setup()
138 info.base_clock / info.base_ahb_ratio / MHZ); in nspire_clk_setup()
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| /drivers/video/fbdev/exynos/ |
| D | exynos_mipi_dsi_common.c | 41 #define MHZ (1000 * 1000) macro
42 #define FIN_HZ (24 * MHZ)
44 #define DFIN_PLL_MIN_HZ (6 * MHZ)
45 #define DFIN_PLL_MAX_HZ (12 * MHZ)
47 #define DFVCO_MIN_HZ (500 * MHZ)
48 #define DFVCO_MAX_HZ (1000 * MHZ)
502 if (dfin_pll < 7 * MHZ) in exynos_mipi_dsi_change_pll()
504 else if (dfin_pll < 8 * MHZ) in exynos_mipi_dsi_change_pll()
506 else if (dfin_pll < 9 * MHZ) in exynos_mipi_dsi_change_pll()
508 else if (dfin_pll < 10 * MHZ) in exynos_mipi_dsi_change_pll()
[all …]
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| /drivers/net/can/softing/ |
| D | softing_cs.c | 37 #define MHZ (1000*1000) macro
44 .freq = 16 * MHZ, .max_brp = 32, .max_sjw = 4,
56 .freq = 16 * MHZ, .max_brp = 32, .max_sjw = 4,
68 .freq = 20 * MHZ, .max_brp = 32, .max_sjw = 4,
80 .freq = 24 * MHZ, .max_brp = 64, .max_sjw = 4,
92 .freq = 16 * MHZ, .max_brp = 64, .max_sjw = 4,
104 .freq = 20 * MHZ, .max_brp = 32, .max_sjw = 4,
116 .freq = 24 * MHZ, .max_brp = 64, .max_sjw = 4,
128 .freq = 16 * MHZ, .max_brp = 64, .max_sjw = 4,
140 .freq = 24 * MHZ, .max_brp = 64, .max_sjw = 4,
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| /drivers/clk/sirf/ |
| D | clk-common.c | 13 #define MHZ (KHZ * KHZ) macro
91 WARN_ON(fin % MHZ); in pll_clk_recalc_rate()
92 return fin / MHZ * nf / nr / od * MHZ; in pll_clk_recalc_rate()
106 rate = rate - rate % MHZ; in pll_clk_round_rate()
108 nf = rate / MHZ; in pll_clk_round_rate()
116 nr = fin / MHZ; in pll_clk_round_rate()
138 nf = rate / MHZ; in pll_clk_set_rate()
139 if (unlikely((rate % MHZ) || nf > BIT(13) || nf < 1)) in pll_clk_set_rate()
143 BUG_ON(fin < MHZ); in pll_clk_set_rate()
145 nr = fin / MHZ; in pll_clk_set_rate()
[all …]
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| /drivers/gpu/drm/exynos/ |
| D | exynos_drm_dsi.c | 524 #ifndef MHZ
525 #define MHZ (1000*1000) macro
539 p_min = DIV_ROUND_UP(fin, (12 * MHZ)); in exynos_dsi_pll_find_pms()
540 p_max = fin / (6 * MHZ); in exynos_dsi_pll_find_pms()
555 if (tmp < 500 * MHZ || in exynos_dsi_pll_find_pms()
556 tmp > driver_data->max_freq * MHZ) in exynos_dsi_pll_find_pms()
608 100 * MHZ, 120 * MHZ, 160 * MHZ, 200 * MHZ, in exynos_dsi_set_pll()
609 270 * MHZ, 320 * MHZ, 390 * MHZ, 450 * MHZ, in exynos_dsi_set_pll()
610 510 * MHZ, 560 * MHZ, 640 * MHZ, 690 * MHZ, in exynos_dsi_set_pll()
611 770 * MHZ, 870 * MHZ, 950 * MHZ, in exynos_dsi_set_pll()
[all …]
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| /drivers/phy/ |
| D | phy-exynos4x12-usb2.c | 143 case 10 * MHZ: in exynos4x12_rate_to_clk()
146 case 12 * MHZ: in exynos4x12_rate_to_clk()
152 case 20 * MHZ: in exynos4x12_rate_to_clk()
155 case 24 * MHZ: in exynos4x12_rate_to_clk()
158 case 50 * MHZ: in exynos4x12_rate_to_clk()
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| D | phy-exynos5250-usb2.c | 153 case 10 * MHZ: in exynos5250_rate_to_clk()
156 case 12 * MHZ: in exynos5250_rate_to_clk()
162 case 20 * MHZ: in exynos5250_rate_to_clk()
165 case 24 * MHZ: in exynos5250_rate_to_clk()
168 case 50 * MHZ: in exynos5250_rate_to_clk()
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| D | phy-s5pv210-usb2.c | 76 case 12 * MHZ: in s5pv210_rate_to_clk()
79 case 24 * MHZ: in s5pv210_rate_to_clk()
82 case 48 * MHZ: in s5pv210_rate_to_clk()
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| D | phy-exynos4210-usb2.c | 111 case 12 * MHZ: in exynos4210_rate_to_clk()
114 case 24 * MHZ: in exynos4210_rate_to_clk()
117 case 48 * MHZ: in exynos4210_rate_to_clk()
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| D | phy-exynos5-usbdrd.c | 122 #define MHZ (KHZ * KHZ) macro
205 case 10 * MHZ: in exynos5_rate_to_clk()
208 case 12 * MHZ: in exynos5_rate_to_clk()
214 case 20 * MHZ: in exynos5_rate_to_clk()
217 case 24 * MHZ: in exynos5_rate_to_clk()
220 case 50 * MHZ: in exynos5_rate_to_clk()
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| D | phy-samsung-usb2.h | 23 #define MHZ (KHZ * KHZ) macro
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| /drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
| D | gk20a.c | 31 #define MHZ (1000 * 1000) macro
163 target_clk_f = rate * 2 / MHZ; in gk20a_pllg_calc_mnp()
164 ref_clk_f = clk->parent_rate / MHZ; in gk20a_pllg_calc_mnp()
259 target_freq = gk20a_pllg_calc_rate(clk) / MHZ; in gk20a_pllg_calc_mnp()
364 clk->parent_rate / MHZ); in _gk20a_pllg_program_mnp()
397 clk->parent_rate / MHZ); in _gk20a_pllg_program_mnp()
456 clk->parent_rate / MHZ); in gk20a_pllg_disable()
668 clk->parent_rate / MHZ); in gk20a_clk_new()
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| /drivers/mfd/ |
| D | sm501.c | 87 #define MHZ (1000 * 1000) macro
122 pll2 = 288 * MHZ; in decode_div()
127 #define fmt_freq(x) ((x) / MHZ), ((x) % MHZ), (x)
145 pll2 = 336 * MHZ; in sm501_dump_clk()
148 pll2 = 288 * MHZ; in sm501_dump_clk()
151 pll2 = 240 * MHZ; in sm501_dump_clk()
154 pll2 = 192 * MHZ; in sm501_dump_clk()
158 sdclk0 = (misct & (1<<12)) ? pll2 : 288 * MHZ; in sm501_dump_clk()
161 sdclk1 = (misct & (1<<20)) ? pll2 : 288 * MHZ; in sm501_dump_clk()
1554 .mclk = 72 * MHZ,
[all …]
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| /drivers/clk/ingenic/ |
| D | cgu.c | 30 #define MHZ (1000 * 1000) macro
137 n = parent_rate / (10 * MHZ); in ingenic_pll_calc()
141 m = (rate / MHZ) * od * n / (parent_rate / MHZ); in ingenic_pll_calc()
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| /drivers/spi/ |
| D | spi-ath79.c | 34 #define MHZ (1000 * 1000) macro
259 rate = DIV_ROUND_UP(clk_get_rate(sp->clk), MHZ); in ath79_spi_probe()
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| /drivers/clk/samsung/ |
| D | clk-s3c2410.c | 385 if (_get_rate("xti") == 12 * MHZ) { in s3c2410_common_clk_init()
395 if (_get_rate("xti") == 12 * MHZ) { in s3c2410_common_clk_init()
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| D | clk-exynos5250.c | 816 if (_get_rate("fin_pll") == 24 * MHZ) { in exynos5250_clk_init()
821 if (_get_rate("mout_vpllsrc") == 24 * MHZ) in exynos5250_clk_init()
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| D | clk.h | 52 #define MHZ (1000 * 1000) macro
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| /drivers/net/wireless/iwlwifi/ |
| D | iwl-nvm-parse.c | 871 CHECK_AND_PRINT_I(40MHZ), in iwl_parse_nvm_mcc_info()
872 CHECK_AND_PRINT_I(80MHZ), in iwl_parse_nvm_mcc_info()
873 CHECK_AND_PRINT_I(160MHZ), in iwl_parse_nvm_mcc_info()
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| D | iwl-eeprom-parse.c | 450 TXP_CHECK_AND_PRINT(40MHZ), in iwl_eeprom_enhanced_txpower()
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| /drivers/staging/sm750fb/ |
| D | sm750.h | 6 #define MHZ(x) ((x) * 1000000) macro
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| /drivers/clk/mediatek/ |
| D | clk-mtk.h | 27 #define MHZ (1000 * 1000) macro
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| D | clk-mt8173.c | 35 FIXED_CLK(CLK_TOP_USB_SYSPLL_125M, "usb_syspll_125m", "clk26m", 125 * MHZ),
1003 #define MT8173_PLL_FMAX (3000UL * MHZ)
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| D | clk-pll.c | 140 unsigned long fmin = 1000 * MHZ; in mtk_pll_calc_values()
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| D | clk-mt8135.c | 601 #define MT8135_PLL_FMAX (2000 * MHZ)
|