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Searched refs:sclk (Results 1 – 25 of 89) sorted by relevance

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/drivers/clk/hisilicon/
Dclkgate-separated.c48 struct clkgate_separated *sclk; in clkgate_separated_enable() local
52 sclk = container_of(hw, struct clkgate_separated, hw); in clkgate_separated_enable()
53 if (sclk->lock) in clkgate_separated_enable()
54 spin_lock_irqsave(sclk->lock, flags); in clkgate_separated_enable()
55 reg = BIT(sclk->bit_idx); in clkgate_separated_enable()
56 writel_relaxed(reg, sclk->enable); in clkgate_separated_enable()
57 readl_relaxed(sclk->enable + CLKGATE_SEPERATED_STATUS); in clkgate_separated_enable()
58 if (sclk->lock) in clkgate_separated_enable()
59 spin_unlock_irqrestore(sclk->lock, flags); in clkgate_separated_enable()
65 struct clkgate_separated *sclk; in clkgate_separated_disable() local
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/drivers/clk/
Dclk-u300.c455 static void syscon_block_reset_enable(struct clk_syscon *sclk) in syscon_block_reset_enable() argument
461 if (!sclk->res_reg) in syscon_block_reset_enable()
464 val = readw(sclk->res_reg); in syscon_block_reset_enable()
465 val |= BIT(sclk->res_bit); in syscon_block_reset_enable()
466 writew(val, sclk->res_reg); in syscon_block_reset_enable()
468 sclk->reset = true; in syscon_block_reset_enable()
471 static void syscon_block_reset_disable(struct clk_syscon *sclk) in syscon_block_reset_disable() argument
477 if (!sclk->res_reg) in syscon_block_reset_disable()
480 val = readw(sclk->res_reg); in syscon_block_reset_disable()
481 val &= ~BIT(sclk->res_bit); in syscon_block_reset_disable()
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Dclk-scpi.c151 struct scpi_clk *sclk, const char *name) in scpi_clk_ops_init() argument
161 sclk->hw.init = &init; in scpi_clk_ops_init()
162 sclk->scpi_ops = get_scpi_ops(); in scpi_clk_ops_init()
165 sclk->info = sclk->scpi_ops->dvfs_get_info(sclk->id); in scpi_clk_ops_init()
166 if (IS_ERR(sclk->info)) in scpi_clk_ops_init()
169 if (sclk->scpi_ops->clk_get_range(sclk->id, &min, &max) || !max) in scpi_clk_ops_init()
175 clk = devm_clk_register(dev, &sclk->hw); in scpi_clk_ops_init()
177 clk_hw_set_rate_range(&sclk->hw, min, max); in scpi_clk_ops_init()
189 struct scpi_clk *sclk; in scpi_of_clk_src_get() local
194 sclk = clk_data->clk[count]; in scpi_of_clk_src_get()
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Dclk-nomadik.c302 struct clk_src *sclk = to_src(hw); in src_clk_enable() local
303 u32 enreg = sclk->group1 ? SRC_PCKEN1 : SRC_PCKEN0; in src_clk_enable()
304 u32 sreg = sclk->group1 ? SRC_PCKSR1 : SRC_PCKSR0; in src_clk_enable()
306 writel(sclk->clkbit, src_base + enreg); in src_clk_enable()
308 while (!(readl(src_base + sreg) & sclk->clkbit)) in src_clk_enable()
315 struct clk_src *sclk = to_src(hw); in src_clk_disable() local
316 u32 disreg = sclk->group1 ? SRC_PCKDIS1 : SRC_PCKDIS0; in src_clk_disable()
317 u32 sreg = sclk->group1 ? SRC_PCKSR1 : SRC_PCKSR0; in src_clk_disable()
319 writel(sclk->clkbit, src_base + disreg); in src_clk_disable()
321 while (readl(src_base + sreg) & sclk->clkbit) in src_clk_disable()
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/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
Dgk104.c68 u32 sclk; in read_pll() local
77 sclk = device->crystal; in read_pll()
81 sclk = read_pll(clk, 0x132020); in read_pll()
85 sclk = read_div(clk, 0, 0x137320, 0x137330); in read_pll()
92 sclk = read_div(clk, (pll & 0xff) / 0x20, 0x137120, 0x137140); in read_pll()
101 sclk = (sclk * N) + (((u16)(fN + 4096) * sclk) >> 13); in read_pll()
102 return sclk / (M * P); in read_pll()
121 u32 sclk = read_vco(clk, dsrc + (doff * 4)); in read_div() local
123 return (sclk * 2) / sdiv; in read_div()
149 u32 sclk, sdiv; in read_clk() local
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Dgf100.c67 u32 sclk; in read_pll() local
75 sclk = device->crystal; in read_pll()
79 sclk = nvkm_clk_read(&clk->base, nv_clk_src_mpllsrc); in read_pll()
82 sclk = nvkm_clk_read(&clk->base, nv_clk_src_mpllsrcref); in read_pll()
88 sclk = read_div(clk, (pll & 0xff) / 0x20, 0x137120, 0x137140); in read_pll()
94 return sclk * N / M / P; in read_pll()
113 u32 sclk = read_vco(clk, dsrc + (doff * 4)); in read_div() local
115 return (sclk * 2) / sdiv; in read_div()
130 u32 sclk, sdiv; in read_clk() local
134 sclk = read_pll(clk, 0x137000 + (idx * 0x20)); in read_clk()
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Dgt215.c64 u32 sctl, sdiv, sclk; in read_clk() local
99 sclk = read_vco(clk, idx); in read_clk()
101 return (sclk * 2) / sdiv; in read_clk()
112 u32 sclk = 0, P = 1, N = 1, M = 1; in read_pll() local
127 sclk = read_clk(clk, 0x00 + idx, false); in read_pll()
130 sclk = read_clk(clk, 0x10 + idx, false); in read_pll()
134 return sclk * N / (M * P); in read_pll()
188 u32 oclk, sclk, sdiv; in gt215_clk_info() local
204 sclk = read_vco(clk, idx); in gt215_clk_info()
205 sdiv = min((sclk * 2) / khz, (u32)65); in gt215_clk_info()
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/drivers/gpu/drm/radeon/
Drv730_dpm.c42 RV770_SMC_SCLK_VALUE *sclk) in rv730_populate_sclk_value() argument
109 sclk->sclk_value = cpu_to_be32(engine_clock); in rv730_populate_sclk_value()
110 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); in rv730_populate_sclk_value()
111 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2); in rv730_populate_sclk_value()
112 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3); in rv730_populate_sclk_value()
113 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(cg_spll_spread_spectrum); in rv730_populate_sclk_value()
114 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(cg_spll_spread_spectrum_2); in rv730_populate_sclk_value()
305 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); in rv730_populate_smc_acpi_state()
306 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2); in rv730_populate_smc_acpi_state()
307 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3); in rv730_populate_smc_acpi_state()
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Dbtc_dpm.c1244 u32 *sclk, u32 *mclk) in btc_skip_blacklist_clocks() argument
1248 if ((sclk == NULL) || (mclk == NULL)) in btc_skip_blacklist_clocks()
1254 if ((btc_blacklist_clocks[i].sclk == *sclk) && in btc_skip_blacklist_clocks()
1261 *sclk = btc_get_valid_sclk(rdev, max_sclk, *sclk + 1); in btc_skip_blacklist_clocks()
1263 if (*sclk < max_sclk) in btc_skip_blacklist_clocks()
1264 btc_skip_blacklist_clocks(rdev, max_sclk, max_mclk, sclk, mclk); in btc_skip_blacklist_clocks()
1274 if ((pl->mclk == 0) || (pl->sclk == 0)) in btc_adjust_clock_combinations()
1277 if (pl->mclk == pl->sclk) in btc_adjust_clock_combinations()
1280 if (pl->mclk > pl->sclk) { in btc_adjust_clock_combinations()
1281 if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > rdev->pm.dpm.dyn_state.mclk_sclk_ratio) in btc_adjust_clock_combinations()
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Drv770_dpm.c272 a_n = (int)state->medium.sclk * pi->lmp + in rv770_populate_smc_t()
273 (int)state->low.sclk * (R600_AH_DFLT - pi->rlp); in rv770_populate_smc_t()
274 a_d = (int)state->low.sclk * (100 - (int)pi->rlp) + in rv770_populate_smc_t()
275 (int)state->medium.sclk * pi->lmp; in rv770_populate_smc_t()
280 a_n = (int)state->high.sclk * pi->lhp + (int)state->medium.sclk * in rv770_populate_smc_t()
282 a_d = (int)state->medium.sclk * (100 - (int)pi->rmp) + in rv770_populate_smc_t()
283 (int)state->high.sclk * pi->lhp; in rv770_populate_smc_t()
486 RV770_SMC_SCLK_VALUE *sclk) in rv770_populate_sclk_value() argument
556 sclk->sclk_value = cpu_to_be32(engine_clock); in rv770_populate_sclk_value()
557 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); in rv770_populate_sclk_value()
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Dtrinity_dpm.c583 u32 index, u32 sclk) in trinity_set_divider_value() argument
591 sclk, false, &dividers); in trinity_set_divider_value()
601 sclk/2, false, &dividers); in trinity_set_divider_value()
721 trinity_set_divider_value(rdev, index, pl->sclk); in trinity_program_power_level()
968 if (new_ps->levels[new_ps->num_levels - 1].sclk >= in trinity_set_uvd_clock_before_set_eng_clock()
969 current_ps->levels[current_ps->num_levels - 1].sclk) in trinity_set_uvd_clock_before_set_eng_clock()
982 if (new_ps->levels[new_ps->num_levels - 1].sclk < in trinity_set_uvd_clock_after_set_eng_clock()
983 current_ps->levels[current_ps->num_levels - 1].sclk) in trinity_set_uvd_clock_after_set_eng_clock()
1333 static u8 trinity_calculate_vce_wm(struct radeon_device *rdev, u32 sclk) in trinity_calculate_vce_wm() argument
1335 if (sclk < 20000) in trinity_calculate_vce_wm()
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Drv740_dpm.c122 RV770_SMC_SCLK_VALUE *sclk) in rv740_populate_sclk_value() argument
177 sclk->sclk_value = cpu_to_be32(engine_clock); in rv740_populate_sclk_value()
178 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); in rv740_populate_sclk_value()
179 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2); in rv740_populate_sclk_value()
180 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3); in rv740_populate_sclk_value()
181 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(cg_spll_spread_spectrum); in rv740_populate_sclk_value()
182 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(cg_spll_spread_spectrum_2); in rv740_populate_sclk_value()
383 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); in rv740_populate_smc_acpi_state()
384 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2); in rv740_populate_smc_acpi_state()
385 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3); in rv740_populate_smc_acpi_state()
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Dni_dpm.c810 if (ps->performance_levels[i].sclk > max_limits->sclk) in ni_apply_state_adjust_rules()
811 ps->performance_levels[i].sclk = max_limits->sclk; in ni_apply_state_adjust_rules()
829 btc_skip_blacklist_clocks(rdev, max_limits->sclk, max_limits->mclk, in ni_apply_state_adjust_rules()
830 &ps->performance_levels[0].sclk, in ni_apply_state_adjust_rules()
834 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk) in ni_apply_state_adjust_rules()
835 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk; in ni_apply_state_adjust_rules()
864 btc_skip_blacklist_clocks(rdev, max_limits->sclk, max_limits->mclk, in ni_apply_state_adjust_rules()
865 &ps->performance_levels[i].sclk, in ni_apply_state_adjust_rules()
874 ps->performance_levels[i].sclk, in ni_apply_state_adjust_rules()
1621 (u8)rv770_calculate_memory_refresh_rate(rdev, pl->sclk); in ni_populate_memory_timing_parameters()
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Dkv_dpm.c534 u32 index, u32 sclk) in kv_set_divider_value() argument
541 sclk, false, &dividers); in kv_set_divider_value()
546 pi->graphics_level[index].SclkFrequency = cpu_to_be32(sclk); in kv_set_divider_value()
723 if (table->entries[i].clk == pi->boot_pl.sclk) in kv_program_bootup_state()
737 if (table->entries[i].sclk_frequency == pi->boot_pl.sclk) in kv_program_bootup_state()
1716 if ((table->entries[i].clk >= new_ps->levels[0].sclk) || in kv_set_valid_clock_range()
1724 if (table->entries[i].clk <= new_ps->levels[new_ps->num_levels - 1].sclk) in kv_set_valid_clock_range()
1730 if ((new_ps->levels[0].sclk - table->entries[pi->highest_valid].clk) > in kv_set_valid_clock_range()
1731 (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk)) in kv_set_valid_clock_range()
1741 if (table->entries[i].sclk_frequency >= new_ps->levels[0].sclk || in kv_set_valid_clock_range()
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Dsumo_dpm.c348 u32 highest_engine_clock = ps->levels[ps->num_levels - 1].sclk; in sumo_program_bsp()
351 highest_engine_clock = pi->boost_pl.sclk; in sumo_program_bsp()
412 m_a = asi * ps->levels[i].sclk / 100; in sumo_program_at()
422 m_a = asi * pi->boost_pl.sclk / 100; in sumo_program_at()
556 pl->sclk, false, &dividers); in sumo_program_power_level()
672 pi->boost_pl.sclk = pi->sys_info.boost_sclk; in sumo_patch_boost_state()
791 pi->acpi_pl.sclk, in sumo_program_acpi_power_level()
845 if (new_ps->levels[new_ps->num_levels - 1].sclk >= in sumo_set_uvd_clock_before_set_eng_clock()
846 current_ps->levels[current_ps->num_levels - 1].sclk) in sumo_set_uvd_clock_before_set_eng_clock()
863 if (new_ps->levels[new_ps->num_levels - 1].sclk < in sumo_set_uvd_clock_after_set_eng_clock()
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Dsi_dpm.c1758 SISLANDS_SMC_SCLK_VALUE *sclk);
2323 prev_sclk = state->performance_levels[i-1].sclk; in si_populate_power_containment_values()
2324 max_sclk = state->performance_levels[i].sclk; in si_populate_power_containment_values()
2343 if (min_sclk < state->performance_levels[0].sclk) in si_populate_power_containment_values()
2344 min_sclk = state->performance_levels[0].sclk; in si_populate_power_containment_values()
2418 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) && in si_populate_sq_ramping_values()
2853 u32 sclk = 0; in si_init_smc_spll_table() local
2866 ret = si_calculate_sclk_params(rdev, sclk, &sclk_params); in si_init_smc_spll_table()
2899 sclk += 512; in si_init_smc_spll_table()
2996 u32 mclk, sclk; in si_apply_state_adjust_rules() local
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/drivers/tty/serial/8250/
D8250_em.c35 struct clk *sclk; member
107 priv->sclk = devm_clk_get(&pdev->dev, "sclk"); in serial8250_em_probe()
108 if (IS_ERR(priv->sclk)) { in serial8250_em_probe()
110 return PTR_ERR(priv->sclk); in serial8250_em_probe()
121 clk_prepare_enable(priv->sclk); in serial8250_em_probe()
122 up.port.uartclk = clk_get_rate(priv->sclk); in serial8250_em_probe()
133 clk_disable_unprepare(priv->sclk); in serial8250_em_probe()
147 clk_disable_unprepare(priv->sclk); in serial8250_em_remove()
/drivers/power/reset/
Dat91-reset.c50 static struct clk *sclk; variable
210 sclk = devm_clk_get(&pdev->dev, NULL); in at91_reset_probe()
211 if (IS_ERR(sclk)) in at91_reset_probe()
212 return PTR_ERR(sclk); in at91_reset_probe()
214 ret = clk_prepare_enable(sclk); in at91_reset_probe()
222 clk_disable_unprepare(sclk); in at91_reset_probe()
234 clk_disable_unprepare(sclk); in at91_reset_remove()
Dat91-poweroff.c55 static struct clk *sclk; variable
165 sclk = devm_clk_get(&pdev->dev, NULL); in at91_poweroff_probe()
166 if (IS_ERR(sclk)) in at91_poweroff_probe()
167 return PTR_ERR(sclk); in at91_poweroff_probe()
169 ret = clk_prepare_enable(sclk); in at91_poweroff_probe()
208 clk_disable_unprepare(sclk); in at91_poweroff_remove()
/drivers/media/dvb-frontends/
Dcx24110.c557 s32 afc; unsigned sclk; in cx24110_get_frontend() local
561 sclk = cx24110_readreg (state, 0x07) & 0x03; in cx24110_get_frontend()
564 if (sclk==0) sclk=90999000L/2L; in cx24110_get_frontend()
565 else if (sclk==1) sclk=60666000L; in cx24110_get_frontend()
566 else if (sclk==2) sclk=80888000L; in cx24110_get_frontend()
567 else sclk=90999000L; in cx24110_get_frontend()
568 sclk>>=8; in cx24110_get_frontend()
569 afc = sclk*(cx24110_readreg (state, 0x44)&0x1f)+ in cx24110_get_frontend()
570 ((sclk*cx24110_readreg (state, 0x45))>>8)+ in cx24110_get_frontend()
571 ((sclk*cx24110_readreg (state, 0x46))>>16); in cx24110_get_frontend()
/drivers/cpufreq/
Dblackfin-cpufreq.c59 static void __init bfin_init_tables(unsigned long cclk, unsigned long sclk) in bfin_init_tables() argument
69 min_cclk = sclk * 2; in bfin_init_tables()
71 min_cclk = sclk; in bfin_init_tables()
180 unsigned long cclk, sclk; in __bfin_cpu_init() local
183 sclk = get_sclk() / 1000; in __bfin_cpu_init()
186 bfin_init_tables(cclk, sclk); in __bfin_cpu_init()
/drivers/i2c/busses/
Di2c-emev2.c73 struct clk *sclk; member
264 priv->sclk = devm_clk_get(&pdev->dev, "sclk"); in em_i2c_probe()
265 if (IS_ERR(priv->sclk)) in em_i2c_probe()
266 return PTR_ERR(priv->sclk); in em_i2c_probe()
268 clk_prepare_enable(priv->sclk); in em_i2c_probe()
300 clk_disable_unprepare(priv->sclk); in em_i2c_probe()
309 clk_disable_unprepare(priv->sclk); in em_i2c_remove()
/drivers/clocksource/
Dtimer-atmel-st.c199 struct clk *sclk; in atmel_st_timer_init() local
224 sclk = of_clk_get(node, 0); in atmel_st_timer_init()
225 if (IS_ERR(sclk)) in atmel_st_timer_init()
228 clk_prepare_enable(sclk); in atmel_st_timer_init()
232 sclk_rate = clk_get_rate(sclk); in atmel_st_timer_init()
/drivers/watchdog/
Dat91sam9_wdt.c94 struct clk *sclk; member
357 wdt->sclk = devm_clk_get(&pdev->dev, NULL); in at91wdt_probe()
358 if (IS_ERR(wdt->sclk)) in at91wdt_probe()
359 return PTR_ERR(wdt->sclk); in at91wdt_probe()
361 err = clk_prepare_enable(wdt->sclk); in at91wdt_probe()
385 clk_disable_unprepare(wdt->sclk); in at91wdt_probe()
397 clk_disable_unprepare(wdt->sclk); in at91wdt_remove()
/drivers/gpu/drm/amd/amdgpu/
Dkv_dpm.c667 u32 index, u32 sclk) in kv_set_divider_value() argument
674 sclk, false, &dividers); in kv_set_divider_value()
679 pi->graphics_level[index].SclkFrequency = cpu_to_be32(sclk); in kv_set_divider_value()
812 if (table->entries[i].clk == pi->boot_pl.sclk) in kv_program_bootup_state()
826 if (table->entries[i].sclk_frequency == pi->boot_pl.sclk) in kv_program_bootup_state()
1812 if ((table->entries[i].clk >= new_ps->levels[0].sclk) || in kv_set_valid_clock_range()
1820 if (table->entries[i].clk <= new_ps->levels[new_ps->num_levels - 1].sclk) in kv_set_valid_clock_range()
1826 if ((new_ps->levels[0].sclk - table->entries[pi->highest_valid].clk) > in kv_set_valid_clock_range()
1827 (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk)) in kv_set_valid_clock_range()
1837 if (table->entries[i].sclk_frequency >= new_ps->levels[0].sclk || in kv_set_valid_clock_range()
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