| /drivers/gpu/drm/tegra/ |
| D | sor.c | 158 int (*probe)(struct tegra_sor *sor);
159 int (*remove)(struct tegra_sor *sor);
217 static inline u32 tegra_sor_readl(struct tegra_sor *sor, unsigned long offset) in tegra_sor_readl() argument
219 return readl(sor->regs + (offset << 2)); in tegra_sor_readl()
222 static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value, in tegra_sor_writel() argument
225 writel(value, sor->regs + (offset << 2)); in tegra_sor_writel()
228 static int tegra_sor_dp_train_fast(struct tegra_sor *sor, in tegra_sor_dp_train_fast() argument
241 tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0); in tegra_sor_dp_train_fast()
247 tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0); in tegra_sor_dp_train_fast()
253 tegra_sor_writel(sor, value, SOR_LANE_POSTCURSOR0); in tegra_sor_dp_train_fast()
[all …]
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| D | Makefile | 13 sor.o \
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| /drivers/gpu/drm/nouveau/nvkm/engine/disp/ |
| D | gm204.c | 43 .sor.nr = 4,
44 .sor.power = nv50_sor_power,
45 .sor.hda_eld = gf119_hda_eld,
46 .sor.hdmi = gk104_hdmi_ctrl,
47 .sor.magic = gm204_sor_magic,
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| D | gk104.c | 43 .sor.nr = 4,
44 .sor.power = nv50_sor_power,
45 .sor.hda_eld = gf119_hda_eld,
46 .sor.hdmi = gk104_hdmi_ctrl,
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| D | gm107.c | 43 .sor.nr = 4,
44 .sor.power = nv50_sor_power,
45 .sor.hda_eld = gf119_hda_eld,
46 .sor.hdmi = gk104_hdmi_ctrl,
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| D | gk110.c | 43 .sor.nr = 4,
44 .sor.power = nv50_sor_power,
45 .sor.hda_eld = gf119_hda_eld,
46 .sor.hdmi = gk104_hdmi_ctrl,
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| D | gt215.c | 45 .sor.nr = 4,
46 .sor.power = nv50_sor_power,
47 .sor.hda_eld = gt215_hda_eld,
48 .sor.hdmi = gt215_hdmi_ctrl,
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| D | g84.c | 44 .sor.nr = 2,
45 .sor.power = nv50_sor_power,
46 .sor.hdmi = g84_hdmi_ctrl,
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| D | gt200.c | 44 .sor.nr = 2,
45 .sor.power = nv50_sor_power,
46 .sor.hdmi = g84_hdmi_ctrl,
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| D | g94.c | 45 .sor.nr = 4,
46 .sor.power = nv50_sor_power,
47 .sor.hdmi = g84_hdmi_ctrl,
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| D | rootnv50.c | 133 return func->sor.power(object, disp, data, size, head, outp); in nv50_disp_root_mthd_()
135 if (!func->sor.hda_eld) in nv50_disp_root_mthd_()
137 return func->sor.hda_eld(object, disp, data, size, head, outp); in nv50_disp_root_mthd_()
139 if (!func->sor.hdmi) in nv50_disp_root_mthd_()
141 return func->sor.hdmi(object, disp, data, size, head, outp); in nv50_disp_root_mthd_()
151 disp->sor.lvdsconf = args->v0.script; in nv50_disp_root_mthd_()
339 for (i = 0; i < disp->func->sor.nr; i++) { in nv50_disp_root_init()
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| D | gf119.c | 165 *conf = disp->sor.lvdsconf; in exec_clkcmp()
325 if (disp->func->sor.magic) in gf119_disp_intr_unk2_2()
326 disp->func->sor.magic(outp); in gf119_disp_intr_unk2_2()
526 .sor.nr = 4,
527 .sor.power = nv50_sor_power,
528 .sor.hda_eld = gf119_hda_eld,
529 .sor.hdmi = gf119_hdmi_ctrl,
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| D | nv50.h | 24 } sor; member
100 } sor; member
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| D | nv50.c | 310 for (i = 0; !(ctrl & (1 << head)) && i < disp->func->sor.nr; i++) in exec_script()
370 for (i = 0; !(ctrl & (1 << head)) && i < disp->func->sor.nr; i++) in exec_clkcmp()
398 *conf = disp->sor.lvdsconf; in exec_clkcmp()
832 .sor.nr = 2,
833 .sor.power = nv50_sor_power,
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| D | dport.c | 334 if (!outp->base.info.location && disp->func->sor.magic) in nvkm_dp_train()
335 disp->func->sor.magic(&outp->base); in nvkm_dp_train()
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| D | rootgf119.c | 106 for (i = 0; i < disp->func->sor.nr; i++) { in gf119_disp_root_init()
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| /drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/ |
| D | dcb.h | 36 struct sor_conf sor; member
45 struct sor_conf sor; member
50 struct sor_conf sor; member
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| /drivers/gpu/drm/nouveau/ |
| D | nouveau_bios.c | 1449 entry->lvdsconf.sor.link = (conf & 0x00000030) >> 4; in parse_dcb20_entry()
1450 link = entry->lvdsconf.sor.link; in parse_dcb20_entry()
1475 entry->dpconf.sor.link = (conf & 0x00000030) >> 4; in parse_dcb20_entry()
1501 link = entry->dpconf.sor.link; in parse_dcb20_entry()
1505 entry->tmdsconf.sor.link = (conf & 0x00000030) >> 4; in parse_dcb20_entry()
1507 link = entry->tmdsconf.sor.link; in parse_dcb20_entry()
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