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Searched refs:dpm (Results 1 – 25 of 38) sorted by relevance

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/drivers/gpu/drm/amd/amdgpu/
Damdgpu_pm.c40 adev->pm.dpm.ac_power = true; in amdgpu_pm_acpi_event_handler()
42 adev->pm.dpm.ac_power = false; in amdgpu_pm_acpi_event_handler()
44 amdgpu_dpm_enable_bapm(adev, adev->pm.dpm.ac_power); in amdgpu_pm_acpi_event_handler()
55 enum amdgpu_pm_state_type pm = adev->pm.dpm.user_state; in amdgpu_get_dpm_state()
72 adev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY; in amdgpu_set_dpm_state()
74 adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED; in amdgpu_set_dpm_state()
76 adev->pm.dpm.user_state = POWER_STATE_TYPE_PERFORMANCE; in amdgpu_set_dpm_state()
98 enum amdgpu_dpm_forced_level level = adev->pm.dpm.forced_level; in amdgpu_get_dpm_forced_performance_level()
127 if (adev->pm.dpm.thermal_active) { in amdgpu_set_dpm_forced_performance_level()
170 temp = adev->pm.dpm.thermal.min_temp; in amdgpu_hwmon_show_temp_thresh()
[all …]
Damdgpu_dpm.c107 if (rps == adev->pm.dpm.current_ps) in amdgpu_dpm_print_ps_status()
109 if (rps == adev->pm.dpm.requested_ps) in amdgpu_dpm_print_ps_status()
111 if (rps == adev->pm.dpm.boot_ps) in amdgpu_dpm_print_ps_status()
297 adev->pm.dpm.platform_caps = le32_to_cpu(power_info->pplib.ulPlatformCaps); in amdgpu_get_platform_caps()
298 adev->pm.dpm.backbias_response_time = le16_to_cpu(power_info->pplib.usBackbiasTime); in amdgpu_get_platform_caps()
299 adev->pm.dpm.voltage_response_time = le16_to_cpu(power_info->pplib.usVoltageTime); in amdgpu_get_platform_caps()
336 adev->pm.dpm.fan.t_hyst = fan_info->fan.ucTHyst; in amdgpu_parse_extended_power_table()
337 adev->pm.dpm.fan.t_min = le16_to_cpu(fan_info->fan.usTMin); in amdgpu_parse_extended_power_table()
338 adev->pm.dpm.fan.t_med = le16_to_cpu(fan_info->fan.usTMed); in amdgpu_parse_extended_power_table()
339 adev->pm.dpm.fan.t_high = le16_to_cpu(fan_info->fan.usTHigh); in amdgpu_parse_extended_power_table()
[all …]
Dci_dpm.c313 struct ci_power_info *pi = adev->pm.dpm.priv; in ci_get_pi()
398 if (adev->pm.dpm.dyn_state.cac_leakage_table.entries == NULL) in ci_populate_bapm_vddc_vid_sidd()
400 if (adev->pm.dpm.dyn_state.cac_leakage_table.count > 8) in ci_populate_bapm_vddc_vid_sidd()
402 if (adev->pm.dpm.dyn_state.cac_leakage_table.count != in ci_populate_bapm_vddc_vid_sidd()
403 adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count) in ci_populate_bapm_vddc_vid_sidd()
406 for (i = 0; i < adev->pm.dpm.dyn_state.cac_leakage_table.count; i++) { in ci_populate_bapm_vddc_vid_sidd()
407 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) { in ci_populate_bapm_vddc_vid_sidd()
408 lo_vid[i] = ci_convert_to_vid(adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1); in ci_populate_bapm_vddc_vid_sidd()
409 hi_vid[i] = ci_convert_to_vid(adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2); in ci_populate_bapm_vddc_vid_sidd()
410 hi2_vid[i] = ci_convert_to_vid(adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3); in ci_populate_bapm_vddc_vid_sidd()
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Dcz_dpm.c57 struct cz_power_info *pi = adev->pm.dpm.priv; in cz_get_pi()
75 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in cz_construct_max_power_limits_table()
167 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac); in cz_parse_sys_info_table()
177 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; in cz_patch_voltage_values()
179 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in cz_patch_voltage_values()
181 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; in cz_patch_voltage_values()
244 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in cz_parse_pplib_clock_info()
278 adev->pm.dpm.boot_ps = rps; in cz_parse_pplib_non_clock_info()
282 adev->pm.dpm.uvd_ps = rps; in cz_parse_pplib_non_clock_info()
331 adev->pm.dpm.ps = kzalloc(sizeof(struct amdgpu_ps) * in cz_parse_power_table()
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Dkv_dpm.c78 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_convert_vid2_to_vid7()
100 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_convert_vid7_to_vid2()
384 struct kv_power_info *pi = adev->pm.dpm.priv; in kv_get_pi()
808 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_program_bootup_state()
910 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; in kv_populate_uvd_table()
983 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in kv_populate_vce_table()
1044 &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table; in kv_populate_samu_table()
1110 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; in kv_populate_acp_table()
1169 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_calculate_dfs_bypass_settings()
1356 kv_update_current_ps(adev, adev->pm.dpm.boot_ps); in kv_dpm_enable()
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Damdgpu_amdkfd.c268 return rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk / 100; in get_max_engine_clock_in_mhz()
/drivers/gpu/drm/radeon/
Dr600_dpm.c145 if (rps == rdev->pm.dpm.current_ps) in r600_dpm_print_ps_status()
147 if (rps == rdev->pm.dpm.requested_ps) in r600_dpm_print_ps_status()
149 if (rps == rdev->pm.dpm.boot_ps) in r600_dpm_print_ps_status()
756 rdev->pm.dpm.thermal.min_temp = low_temp; in r600_set_thermal_temperature_range()
757 rdev->pm.dpm.thermal.max_temp = high_temp; in r600_set_thermal_temperature_range()
856 rdev->pm.dpm.platform_caps = le32_to_cpu(power_info->pplib.ulPlatformCaps); in r600_get_platform_caps()
857 rdev->pm.dpm.backbias_response_time = le16_to_cpu(power_info->pplib.usBackbiasTime); in r600_get_platform_caps()
858 rdev->pm.dpm.voltage_response_time = le16_to_cpu(power_info->pplib.usVoltageTime); in r600_get_platform_caps()
893 rdev->pm.dpm.fan.t_hyst = fan_info->fan.ucTHyst; in r600_parse_extended_power_table()
894 rdev->pm.dpm.fan.t_min = le16_to_cpu(fan_info->fan.usTMin); in r600_parse_extended_power_table()
[all …]
Dradeon_pm.c74 rdev->pm.dpm.ac_power = true; in radeon_pm_acpi_event_handler()
76 rdev->pm.dpm.ac_power = false; in radeon_pm_acpi_event_handler()
78 if (rdev->asic->dpm.enable_bapm) in radeon_pm_acpi_event_handler()
79 radeon_dpm_enable_bapm(rdev, rdev->pm.dpm.ac_power); in radeon_pm_acpi_event_handler()
459 enum radeon_pm_state_type pm = rdev->pm.dpm.user_state; in radeon_get_dpm_state()
476 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY; in radeon_set_dpm_state()
478 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED; in radeon_set_dpm_state()
480 rdev->pm.dpm.user_state = POWER_STATE_TYPE_PERFORMANCE; in radeon_set_dpm_state()
503 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level; in radeon_get_dpm_forced_performance_level()
540 if (rdev->asic->dpm.force_performance_level) { in radeon_set_dpm_forced_performance_level()
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Dbtc_dpm.c1231 return btc_find_valid_clock(&rdev->pm.dpm.dyn_state.valid_mclk_values, in btc_get_valid_mclk()
1238 return btc_find_valid_clock(&rdev->pm.dpm.dyn_state.valid_sclk_values, in btc_get_valid_sclk()
1281 if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > rdev->pm.dpm.dyn_state.mclk_sclk_ratio) in btc_adjust_clock_combinations()
1285 (rdev->pm.dpm.dyn_state.mclk_sclk_ratio - 1)) / in btc_adjust_clock_combinations()
1286 rdev->pm.dpm.dyn_state.mclk_sclk_ratio); in btc_adjust_clock_combinations()
1288 if ((pl->sclk - pl->mclk) > rdev->pm.dpm.dyn_state.sclk_mclk_delta) in btc_adjust_clock_combinations()
1292 rdev->pm.dpm.dyn_state.sclk_mclk_delta); in btc_adjust_clock_combinations()
1319 if ((*vddc - *vddci) > rdev->pm.dpm.dyn_state.vddc_vddci_delta) { in btc_apply_voltage_delta_rules()
1321 (*vddc - rdev->pm.dpm.dyn_state.vddc_vddci_delta)); in btc_apply_voltage_delta_rules()
1325 if ((*vddci - *vddc) > rdev->pm.dpm.dyn_state.vddc_vddci_delta) { in btc_apply_voltage_delta_rules()
[all …]
Dci_dpm.c195 struct ci_power_info *pi = rdev->pm.dpm.priv; in ci_get_pi()
280 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries == NULL) in ci_populate_bapm_vddc_vid_sidd()
282 if (rdev->pm.dpm.dyn_state.cac_leakage_table.count > 8) in ci_populate_bapm_vddc_vid_sidd()
284 if (rdev->pm.dpm.dyn_state.cac_leakage_table.count != in ci_populate_bapm_vddc_vid_sidd()
285 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count) in ci_populate_bapm_vddc_vid_sidd()
288 for (i = 0; i < rdev->pm.dpm.dyn_state.cac_leakage_table.count; i++) { in ci_populate_bapm_vddc_vid_sidd()
289 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) { in ci_populate_bapm_vddc_vid_sidd()
290 lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1); in ci_populate_bapm_vddc_vid_sidd()
291 hi_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2); in ci_populate_bapm_vddc_vid_sidd()
292 hi2_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3); in ci_populate_bapm_vddc_vid_sidd()
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Dsi_dpm.c1765 struct si_power_info *pi = rdev->pm.dpm.priv; in si_get_pi()
1839 u32 p_limit1 = rdev->pm.dpm.tdp_limit; in si_update_dte_from_pl2()
1840 u32 p_limit2 = rdev->pm.dpm.near_tdp_limit; in si_update_dte_from_pl2()
2130 if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit) in si_calculate_adjusted_tdp_limits()
2133 max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100; in si_calculate_adjusted_tdp_limits()
2136 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; in si_calculate_adjusted_tdp_limits()
2137 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit); in si_calculate_adjusted_tdp_limits()
2139 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; in si_calculate_adjusted_tdp_limits()
2140 adjustment_delta = rdev->pm.dpm.tdp_limit - *tdp_limit; in si_calculate_adjusted_tdp_limits()
2141 if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted) in si_calculate_adjusted_tdp_limits()
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Drv6xx_dpm.c46 struct rv6xx_power_info *pi = rdev->pm.dpm.priv; in rv6xx_get_pi()
922 rdev->pm.dpm.voltage_response_time, in rv6xx_program_voltage_timing_parameters()
926 rdev->pm.dpm.backbias_response_time, in rv6xx_program_voltage_timing_parameters()
1186 if (rdev->pm.dpm.new_active_crtcs & 1) { in rv6xx_program_display_gap()
1189 } else if (rdev->pm.dpm.new_active_crtcs & 2) { in rv6xx_program_display_gap()
1299 msleep((rdev->pm.dpm.voltage_response_time + 999) / 1000); in rv6xx_step_sw_voltage()
1549 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; in rv6xx_dpm_enable()
1554 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS) in rv6xx_dpm_enable()
1616 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; in rv6xx_dpm_disable()
1634 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS) in rv6xx_dpm_disable()
[all …]
Dkv_dpm.c251 struct kv_power_info *pi = rdev->pm.dpm.priv; in kv_get_pi()
556 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_convert_vid2_to_vid7()
578 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_convert_vid7_to_vid2()
719 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_program_bootup_state()
821 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; in kv_populate_uvd_table()
894 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in kv_populate_vce_table()
955 &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table; in kv_populate_samu_table()
1021 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; in kv_populate_acp_table()
1080 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_calculate_dfs_bypass_settings()
1280 kv_update_current_ps(rdev, rdev->pm.dpm.boot_ps); in kv_dpm_enable()
[all …]
Dni_dpm.c728 struct ni_power_info *pi = rdev->pm.dpm.priv; in ni_get_pi()
795 if ((rdev->pm.dpm.new_active_crtc_count > 1) || in ni_apply_state_adjust_rules()
801 if (rdev->pm.dpm.ac_power) in ni_apply_state_adjust_rules()
802 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in ni_apply_state_adjust_rules()
804 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; in ni_apply_state_adjust_rules()
806 if (rdev->pm.dpm.ac_power == false) { in ni_apply_state_adjust_rules()
873 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in ni_apply_state_adjust_rules()
876 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, in ni_apply_state_adjust_rules()
879 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in ni_apply_state_adjust_rules()
882 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk, in ni_apply_state_adjust_rules()
[all …]
Drs780_dpm.c43 struct igp_power_info *pi = rdev->pm.dpm.priv; in rs780_get_pi()
380 struct igp_ps *current_state = rs780_get_ps(rdev->pm.dpm.current_ps); in rs780_force_voltage()
407 struct igp_ps *current_state = rs780_get_ps(rdev->pm.dpm.current_ps); in rs780_force_fbdiv()
600 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; in rs780_dpm_enable()
652 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps; in rs780_dpm_set_power_state()
653 struct radeon_ps *old_ps = rdev->pm.dpm.current_ps; in rs780_dpm_set_power_state()
742 rdev->pm.dpm.boot_ps = rps; in rs780_parse_pplib_non_clock_info()
744 rdev->pm.dpm.uvd_ps = rps; in rs780_parse_pplib_non_clock_info()
807 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) * in rs780_parse_power_table()
809 if (!rdev->pm.dpm.ps) in rs780_parse_power_table()
[all …]
Dtrinity_dpm.c356 struct trinity_power_info *pi = rdev->pm.dpm.priv; in trinity_get_pi()
1060 rdev->pm.dpm.thermal.min_temp = low_temp; in trinity_set_thermal_temperature_range()
1061 rdev->pm.dpm.thermal.max_temp = high_temp; in trinity_set_thermal_temperature_range()
1123 trinity_update_current_ps(rdev, rdev->pm.dpm.boot_ps); in trinity_dpm_enable()
1171 trinity_update_current_ps(rdev, rdev->pm.dpm.boot_ps); in trinity_dpm_disable()
1226 rdev->pm.dpm.forced_level = level; in trinity_dpm_force_performance_level()
1234 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps; in trinity_dpm_pre_set_power_state()
1255 trinity_dpm_bapm_enable(rdev, rdev->pm.dpm.ac_power); in trinity_dpm_set_power_state()
1509 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in trinity_get_vce_clock_voltage()
1546 u32 num_active_displays = rdev->pm.dpm.new_active_crtc_count; in trinity_apply_state_adjust_rules()
[all …]
Drv770_dpm.c57 struct rv7xx_power_info *pi = rdev->pm.dpm.priv; in rv770_get_pi()
64 struct evergreen_power_info *pi = rdev->pm.dpm.priv; in evergreen_get_pi()
1191 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) { in rv770_init_smc_table()
1194 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_DONT_WAIT_FOR_VBLANK_ON_ALERT) in rv770_init_smc_table()
1197 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_GOTO_BOOT_ON_ALERT) in rv770_init_smc_table()
1201 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) in rv770_init_smc_table()
1347 if (rdev->pm.dpm.new_active_crtcs & 1) { in rv770_program_display_gap()
1350 } else if (rdev->pm.dpm.new_active_crtcs & 2) { in rv770_program_display_gap()
1499 rdev->pm.dpm.forced_level = level; in rv770_dpm_force_performance_level()
1708 voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time; in rv770_program_response_times()
[all …]
Dcypress_dpm.c1635 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) in cypress_init_smc_table()
1638 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) in cypress_init_smc_table()
1641 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) in cypress_init_smc_table()
1748 if (rdev->pm.dpm.new_active_crtc_count > 0) in cypress_program_display_gap()
1753 if (rdev->pm.dpm.new_active_crtc_count > 1) in cypress_program_display_gap()
1763 if ((rdev->pm.dpm.new_active_crtc_count > 0) && in cypress_program_display_gap()
1764 (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) { in cypress_program_display_gap()
1767 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) in cypress_program_display_gap()
1780 cypress_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0); in cypress_program_display_gap()
1807 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; in cypress_dpm_enable()
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Dsumo_dpm.c84 struct sumo_power_info *pi = rdev->pm.dpm.priv; in sumo_get_pi()
1175 rdev->pm.dpm.thermal.min_temp = low_temp; in sumo_set_thermal_temperature_range()
1176 rdev->pm.dpm.thermal.max_temp = high_temp; in sumo_set_thermal_temperature_range()
1233 sumo_update_current_ps(rdev, rdev->pm.dpm.boot_ps); in sumo_dpm_enable()
1278 sumo_update_current_ps(rdev, rdev->pm.dpm.boot_ps); in sumo_dpm_disable()
1284 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps; in sumo_dpm_pre_set_power_state()
1423 rdev->pm.dpm.boot_ps = rps; in sumo_parse_pplib_non_clock_info()
1427 rdev->pm.dpm.uvd_ps = rps; in sumo_parse_pplib_non_clock_info()
1485 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) * in sumo_parse_power_table()
1487 if (!rdev->pm.dpm.ps) in sumo_parse_power_table()
[all …]
Dradeon.h1663 struct radeon_dpm dpm; member
1996 } dpm; member
2783 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2784 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2785 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
2786 #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
2787 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
2788 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
2789 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
2790 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
[all …]
Dradeon_uvd.c828 radeon_uvd_count_handles(rdev, &rdev->pm.dpm.sd, in radeon_uvd_idle_work_handler()
829 &rdev->pm.dpm.hd); in radeon_uvd_idle_work_handler()
850 if ((rdev->pm.dpm.sd != sd) || in radeon_uvd_note_usage()
851 (rdev->pm.dpm.hd != hd)) { in radeon_uvd_note_usage()
852 rdev->pm.dpm.sd = sd; in radeon_uvd_note_usage()
853 rdev->pm.dpm.hd = hd; in radeon_uvd_note_usage()
Dradeon_asic.c1083 .dpm = {
1176 .dpm = {
1282 .dpm = {
1402 .dpm = {
1496 .dpm = {
1589 .dpm = {
1737 .dpm = {
1858 .dpm = {
1996 .dpm = {
2166 .dpm = {
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/drivers/isdn/sc/
Dmessage.c30 DualPortMemory *dpm; in receivemessage() local
51 dpm = (DualPortMemory *) sc_adapter[card]->rambase; in receivemessage()
52 memcpy_fromio(rspmsg, &(dpm->rsp_queue[dpm->rsp_tail]), in receivemessage()
54 dpm->rsp_tail = (dpm->rsp_tail + 1) % MAX_MESSAGES; in receivemessage()
92 DualPortMemory *dpm; in sendmessage() local
146 dpm = (DualPortMemory *) sc_adapter[card]->rambase; /* Fix me */ in sendmessage()
147 memcpy_toio(&(dpm->req_queue[dpm->req_head]), &sndmsg, MSG_LEN); in sendmessage()
148 dpm->req_head = (dpm->req_head + 1) % MAX_MESSAGES; in sendmessage()
Dinit.c440 DualPortMemory *dpm; in identify_board() local
510 dpm = (DualPortMemory *) rambase; in identify_board()
517 memcpy_toio(&(dpm->req_queue[dpm->req_head++]), &sndmsg, MSG_LEN); in identify_board()
533 memcpy_fromio(&rcvmsg, &(dpm->rsp_queue[dpm->rsp_tail]), MSG_LEN); in identify_board()
/drivers/net/can/
Djanz-ican3.c215 void __iomem *dpm; member
302 peer = ioread8(mod->dpm + MSYNC_PEER); in ican3_old_recv_msg()
303 locl = ioread8(mod->dpm + MSYNC_LOCL); in ican3_old_recv_msg()
320 memcpy_fromio(msg, mod->dpm, sizeof(*msg)); in ican3_old_recv_msg()
329 iowrite8(locl, mod->dpm + MSYNC_LOCL); in ican3_old_recv_msg()
347 peer = ioread8(mod->dpm + MSYNC_PEER); in ican3_old_send_msg()
348 locl = ioread8(mod->dpm + MSYNC_LOCL); in ican3_old_send_msg()
362 memcpy_toio(mod->dpm, msg, sizeof(*msg)); in ican3_old_send_msg()
369 iowrite8(locl, mod->dpm + MSYNC_LOCL); in ican3_old_send_msg()
392 dst = mod->dpm; in ican3_init_new_host_interface()
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