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Searched refs:sel (Results 1 – 25 of 54) sorted by relevance

123

/arch/mips/include/asm/netlogic/
Dmips-extns.h174 #define __read_64bit_c2_split(source, sel) \ argument
180 if (sel == 0) \
192 "dmfc2\t%M0, " #source ", " #sel "\n\t" \
203 #define __write_64bit_c2_split(source, sel, val) \ argument
208 if (sel == 0) \
225 "dmtc2\t%L0, " #source ", " #sel "\n\t" \
231 #define __read_32bit_c2_register(source, sel) \ argument
233 if (sel == 0) \
242 "mfc2\t%0, " #source ", " #sel "\n\t" \
248 #define __read_64bit_c2_register(source, sel) \ argument
[all …]
/arch/arm/mach-dove/
Dmpp.c71 static void __init dove_mpp_cfg_nfc(int sel) in dove_mpp_cfg_nfc() argument
76 mpp_gen_cfg |= sel; in dove_mpp_cfg_nfc()
82 static void __init dove_mpp_cfg_au1(int sel) in dove_mpp_cfg_au1() argument
94 if (!sel || sel == 0x2) in dove_mpp_cfg_au1()
99 if (sel & 0x1) { in dove_mpp_cfg_au1()
103 if (sel & 0x2) { in dove_mpp_cfg_au1()
107 if (sel & 0x4) { in dove_mpp_cfg_au1()
111 if (sel & 0x8) in dove_mpp_cfg_au1()
129 unsigned int sel = MPP_SEL(*mpp_grp_list); in dove_mpp_conf_grp() local
137 mpp_ctrl4 |= sel << num; in dove_mpp_conf_grp()
[all …]
/arch/x86/kernel/
Dtls.c117 unsigned short __maybe_unused sel, modified_sel; in do_set_thread_area() local
154 savesegment(ds, sel); in do_set_thread_area()
155 if (sel == modified_sel) in do_set_thread_area()
156 loadsegment(ds, sel); in do_set_thread_area()
158 savesegment(es, sel); in do_set_thread_area()
159 if (sel == modified_sel) in do_set_thread_area()
160 loadsegment(es, sel); in do_set_thread_area()
162 savesegment(fs, sel); in do_set_thread_area()
163 if (sel == modified_sel) in do_set_thread_area()
164 loadsegment(fs, sel); in do_set_thread_area()
[all …]
Dprocess_64.c198 unsigned short sel) in loadseg() argument
201 loadsegment(fs, sel); in loadseg()
203 load_gs_index(sel); in loadseg()
/arch/mips/kvm/
Ddyntrans.c91 u32 rd, sel; in kvm_mips_trans_mfc0() local
94 sel = inst.c0r_format.sel; in kvm_mips_trans_mfc0()
96 if (rd == MIPS_CP0_ERRCTL && sel == 0) { in kvm_mips_trans_mfc0()
104 offsetof(struct kvm_mips_commpage, cop0.reg[rd][sel]); in kvm_mips_trans_mfc0()
118 u32 rd, sel; in kvm_mips_trans_mtc0() local
121 sel = inst.c0r_format.sel; in kvm_mips_trans_mtc0()
126 offsetof(struct kvm_mips_commpage, cop0.reg[rd][sel]); in kvm_mips_trans_mtc0()
Demulate.c1060 u32 rt, rd, sel; in kvm_mips_emulate_CP0() local
1100 sel = inst.c0r_format.sel; in kvm_mips_emulate_CP0()
1105 cop0->stat[rd][sel]++; in kvm_mips_emulate_CP0()
1108 if ((rd == MIPS_CP0_COUNT) && (sel == 0)) { in kvm_mips_emulate_CP0()
1111 } else if ((rd == MIPS_CP0_ERRCTL) && (sel == 0)) { in kvm_mips_emulate_CP0()
1117 vcpu->arch.gprs[rt] = (s32)cop0->reg[rd][sel]; in kvm_mips_emulate_CP0()
1125 KVM_TRACE_COP0(rd, sel), in kvm_mips_emulate_CP0()
1130 vcpu->arch.gprs[rt] = cop0->reg[rd][sel]; in kvm_mips_emulate_CP0()
1133 KVM_TRACE_COP0(rd, sel), in kvm_mips_emulate_CP0()
1139 cop0->stat[rd][sel]++; in kvm_mips_emulate_CP0()
[all …]
/arch/powerpc/perf/
Dmpc7450-pmu.c83 int pmc, sel; in mpc7450_threshold_use() local
86 sel = event & PM_PMCSEL_MSK; in mpc7450_threshold_use()
89 if (sel == 0x1e || sel == 0x1f) in mpc7450_threshold_use()
91 if (sel == 0x28 || sel == 0x2b) in mpc7450_threshold_use()
95 if (sel == 0x20) in mpc7450_threshold_use()
99 if (sel == 0xc || sel == 0xd) in mpc7450_threshold_use()
101 if (sel == 0x11) in mpc7450_threshold_use()
105 if (sel == 0x10) in mpc7450_threshold_use()
/arch/mips/include/asm/
Dmipsmtregs.h284 #define mftc0(rt,sel) \ argument
292 " # mftc0 $1, $" #rt ", " #sel " \n" \
293 " .word 0x41000800 | (" #rt " << 16) | " #sel " \n" \
318 #define mftr(rt, u, sel) \ argument
323 " mftr %0, " #rt ", " #u ", " #sel " \n" \
342 #define mttc0(rd, sel, v) \ argument
349 " # mttc0 %0," #rd ", " #sel " \n" \
350 " .word 0x41810000 | (" #rd " << 11) | " #sel " \n" \
357 #define mttr(rd, u, sel, v) \ argument
360 "mttr %0," #rd ", " #u ", " #sel \
Dmipsregs.h1174 #define __read_32bit_c0_register(source, sel) \ argument
1176 if (sel == 0) \
1183 "mfc0\t%0, " #source ", " #sel "\n\t" \
1189 #define __read_64bit_c0_register(source, sel) \ argument
1192 __res = __read_64bit_c0_split(source, sel); \
1193 else if (sel == 0) \
1202 "dmfc0\t%0, " #source ", " #sel "\n\t" \
1208 #define __write_32bit_c0_register(register, sel, value) \ argument
1210 if (sel == 0) \
1217 "mtc0\t%z0, " #register ", " #sel "\n\t" \
[all …]
Dasmmacro.h233 .macro MFTR rt=0, rd=0, u=0, sel=0
234 .word 0x41000000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)
237 .macro MTTR rt=0, rd=0, u=0, sel=0
238 .word 0x41800000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)
/arch/alpha/kernel/
Dtime.c205 unsigned char x, sel = 0; in common_init_rtc() local
213 sel = RTC_REF_CLCK_32KHZ + 6; in common_init_rtc()
216 sel = RTC_REF_CLCK_32KHZ + __builtin_ffs(32768 / CONFIG_HZ); in common_init_rtc()
220 if (sel) { in common_init_rtc()
222 CONFIG_HZ, sel); in common_init_rtc()
223 CMOS_WRITE(sel, RTC_FREQ_SELECT); in common_init_rtc()
/arch/arm/plat-orion/
Dmpp.c43 unsigned int sel = MPP_SEL(*mpp_list); in orion_mpp_conf() local
60 mpp_ctrl[num / 8] |= sel << shift; in orion_mpp_conf()
/arch/x86/boot/
Dvideo.c205 unsigned int sel; in mode_menu() local
226 sel = get_entry(); in mode_menu()
227 if (sel != SCAN) in mode_menu()
228 return sel; in mode_menu()
/arch/x86/oprofile/
Dop_model_p4.c353 #define ESCR_SET_EVENT_SELECT(escr, sel) ((escr) |= (((sel) & 0x3f) << 25)) argument
359 #define CCCR_SET_ESCR_SELECT(cccr, sel) ((cccr) |= (((sel) & 0x07) << 13)) argument
/arch/arm/boot/dts/
Dtegra124-jetson-tk1-emc.dtsi101 nvidia,emc-sel-dpd-ctrl = <0x00040128>;
269 nvidia,emc-sel-dpd-ctrl = <0x00040128>;
437 nvidia,emc-sel-dpd-ctrl = <0x00040128>;
605 nvidia,emc-sel-dpd-ctrl = <0x00040128>;
773 nvidia,emc-sel-dpd-ctrl = <0x00040128>;
941 nvidia,emc-sel-dpd-ctrl = <0x00040128>;
1109 nvidia,emc-sel-dpd-ctrl = <0x00040128>;
1277 nvidia,emc-sel-dpd-ctrl = <0x00040008>;
1445 nvidia,emc-sel-dpd-ctrl = <0x00040008>;
1613 nvidia,emc-sel-dpd-ctrl = <0x00040008>;
[all …]
Dtegra124-nyan-blaze-emc.dtsi90 nvidia,emc-sel-dpd-ctrl = <0x00040128>;
258 nvidia,emc-sel-dpd-ctrl = <0x00040128>;
426 nvidia,emc-sel-dpd-ctrl = <0x00040128>;
594 nvidia,emc-sel-dpd-ctrl = <0x00040128>;
762 nvidia,emc-sel-dpd-ctrl = <0x00040128>;
930 nvidia,emc-sel-dpd-ctrl = <0x00040008>;
1098 nvidia,emc-sel-dpd-ctrl = <0x00040128>;
1266 nvidia,emc-sel-dpd-ctrl = <0x00040008>;
1434 nvidia,emc-sel-dpd-ctrl = <0x00040008>;
1602 nvidia,emc-sel-dpd-ctrl = <0x00040000>;
Dtegra124-nyan-big-emc.dtsi90 nvidia,emc-sel-dpd-ctrl = <0x00040128>;
258 nvidia,emc-sel-dpd-ctrl = <0x00040128>;
426 nvidia,emc-sel-dpd-ctrl = <0x00040128>;
594 nvidia,emc-sel-dpd-ctrl = <0x00040128>;
762 nvidia,emc-sel-dpd-ctrl = <0x00040128>;
930 nvidia,emc-sel-dpd-ctrl = <0x00040008>;
1098 nvidia,emc-sel-dpd-ctrl = <0x00040128>;
1266 nvidia,emc-sel-dpd-ctrl = <0x00040008>;
1434 nvidia,emc-sel-dpd-ctrl = <0x00040008>;
1602 nvidia,emc-sel-dpd-ctrl = <0x00040000>;
Dtegra124-apalis-emc.dtsi142 nvidia,emc-sel-dpd-ctrl = <0x00040128>;
239 nvidia,emc-sel-dpd-ctrl = <0x00040128>;
336 nvidia,emc-sel-dpd-ctrl = <0x00040128>;
433 nvidia,emc-sel-dpd-ctrl = <0x00040128>;
530 nvidia,emc-sel-dpd-ctrl = <0x00040128>;
627 nvidia,emc-sel-dpd-ctrl = <0x00040128>;
724 nvidia,emc-sel-dpd-ctrl = <0x00040128>;
821 nvidia,emc-sel-dpd-ctrl = <0x00040008>;
918 nvidia,emc-sel-dpd-ctrl = <0x00040008>;
1015 nvidia,emc-sel-dpd-ctrl = <0x00040008>;
[all …]
Domap2420-n8x0-common.dtsi14 &gpio3 0 GPIO_ACTIVE_HIGH /* gpio64 sel */
Dsocfpga_cyclone5_mcvevk.dts77 ts,ref-sel = <0>;
Dimx53-m53.dtsi70 st,ref-sel = <0>;
Ddm814x.dtsi553 phy_sel: cpsw-phy-sel@48140650 {
554 compatible = "ti,am3352-cpsw-phy-sel";
556 reg-names = "gmii-sel";
/arch/cris/include/arch-v32/arch/hwregs/
Data_defs.h121 unsigned int sel : 2; member
/arch/mips/include/asm/octeon/
Dcvmx-gpio-defs.h356 uint64_t sel:4; member
358 uint64_t sel:4;
/arch/mips/include/uapi/asm/
Dinst.h664 __BITFIELD_FIELD(unsigned int sel : 3,
676 __BITFIELD_FIELD(unsigned int sel : 3,
739 __BITFIELD_FIELD(unsigned int sel : 4,

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