| /arch/mips/power/ |
| D | hibernate_asm.S | 16 PTR_LA t0, saved_regs
17 PTR_S ra, PT_R31(t0)
18 PTR_S sp, PT_R29(t0)
19 PTR_S fp, PT_R30(t0)
20 PTR_S gp, PT_R28(t0)
21 PTR_S s0, PT_R16(t0)
22 PTR_S s1, PT_R17(t0)
23 PTR_S s2, PT_R18(t0)
24 PTR_S s3, PT_R19(t0)
25 PTR_S s4, PT_R20(t0)
[all …]
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| /arch/mips/kernel/ |
| D | r2300_switch.S | 99 mfc0 t0, CP0_STATUS
101 or t0, t1
102 mtc0 t0, CP0_STATUS
106 li t0, -1
108 mtc1 t0, $f0
109 mtc1 t0, $f1
110 mtc1 t0, $f2
111 mtc1 t0, $f3
112 mtc1 t0, $f4
113 mtc1 t0, $f5
[all …]
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| D | cps-vec.S | 120 li t0, CAUSEF_IV
121 mtc0 t0, CP0_CAUSE
124 li t0, ST0_CU1 | ST0_CU0 | ST0_BEV | STATUS_BITDEPS
125 mtc0 t0, CP0_STATUS
138 li t0, 0xff
139 sw t0, GCR_CL_COHERENCE_OFS(v1)
143 1: mfc0 t0, CP0_CONFIG
144 ori t0, 0x7
145 xori t0, 0x7
146 or t0, t0, s0
[all …]
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| D | bmips_5xxx_init.S | 33 and t0, kva, t2 ; \
36 9: cache op, 0(t0) ; \
37 bne t0, t1, 9b ; \
38 addu t0, linesize ; \
123 move t0, a0
150 move a0, t0
178 move a0, t0
216 move t0, a0
242 move a0, t0
269 move a0, t0
[all …]
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| D | octeon_switch.S | 33 dmfc0 t0, $11,7 /* CvmMemCtl */
34 bbit0 t0, 6, 3f /* Is user access enabled? */
38 andi t0, 0x3f
40 sll t0, 7-LONGLOG-1
47 subu t0, 1 /* Decrement loop var */
52 bnez t0, 2b /* Loop until we've copied it all */
57 dmfc0 t0, $11,7 /* CvmMemCtl */
58 xori t0, t0, 0x40 /* Bit 6 is CVMSEG user enable */
59 dmtc0 t0, $11,7 /* CvmMemCtl */
76 PTR_ADDU t0, $28, _THREAD_SIZE - 32
[all …]
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| D | entry.S | 43 LONG_L t0, PT_STATUS(sp) # returning to kernel mode?
44 andi t0, t0, KU_USER
45 beqz t0, resume_kernel
57 andi t0, a2, _TIF_WORK_MASK # (ignoring syscall_trace)
58 bnez t0, work_pending
64 lw t0, TI_PRE_COUNT($28)
65 bnez t0, restore_all
67 LONG_L t0, TI_FLAGS($28)
68 andi t1, t0, _TIF_NEED_RESCHED
70 LONG_L t0, PT_STATUS(sp) # Interrupts off?
[all …]
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| D | head.S | 37 mfc0 t0, CP0_STATUS
38 or t0, ST0_CU0|\set|0x1f|\clr
39 xor t0, 0x1f|\clr
40 mtc0 t0, CP0_STATUS
92 PTR_LA t0, 0f
93 jr t0
105 lw t0, (t2)
106 beq t0, t1, dtb_found
115 PTR_LA t0, __bss_start # clear .bss
116 LONG_S zero, (t0)
[all …]
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| /arch/mips/include/asm/mach-loongson64/ |
| D | kernel-entry-init.h | 22 mfc0 t0, $16, 3
23 or t0, (0x1 << 7)
24 mtc0 t0, $16, 3
26 mfc0 t0, $5, 1
27 or t0, (0x1 << 29)
28 mtc0 t0, $5, 1
31 mfc0 t0, $16, 6
32 or t0, 0x100
33 mtc0 t0, $16, 6
48 mfc0 t0, $16, 3
[all …]
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| /arch/mips/netlogic/common/ |
| D | reset.S | 59 li t0, LSU_DEFEATURE
60 mfcr t1, t0
64 mtcr t1, t0
66 li t0, ICU_DEFEATURE
67 mfcr t1, t0
69 mtcr t1, t0
71 li t0, SCHED_DEFEATURE
73 mtcr t1, t0
82 mfc0 t0, CP0_PAGEMASK, 1
84 or t0, t1
[all …]
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| D | smpboot.S | 61 li t0, CKSEG1ADDR(RESET_VEC_PHYS)
65 daddu t2, t0
89 PTR_LA t0, nlm_early_init_secondary
90 jalr t0
93 PTR_LA t0, smp_bootstrap
94 jr t0
105 mfc0 t0, $15, 1 /* read ebase */
106 andi t0, 0x1f /* t0 has the processor_id() */
107 andi t2, t0, 0x3 /* thread num */
108 sll t0, 2 /* offset in cpu array */
[all …]
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| /arch/mips/include/asm/mach-ip27/ |
| D | kernel-entry-init.h | 44 dli t0, 0xffffffffc0000000
45 dmtc0 t0, CP0_ENTRYHI
46 li t0, 0x1c000 # Offset of text into node memory
49 or t1, t1, t0 # Physical load address of kernel text
50 or t2, t2, t0 # Physical load address of kernel data
55 li t0, ((PAGE_GLOBAL | PAGE_VALID | CACHE_CACHABLE_COW) >> 6)
56 or t0, t0, t1
57 mtc0 t0, CP0_ENTRYLO0 # physaddr, VG, cach exlwr
58 li t0, ((PAGE_GLOBAL | PAGE_VALID | PAGE_DIRTY | CACHE_CACHABLE_COW) >> 6)
59 or t0, t0, t2
[all …]
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| /arch/arm/crypto/ |
| D | sha512-armv4.pl | 66 $t0="r9";
90 mov $t0,$Elo,lsr#14
94 eor $t0,$t0,$Ehi,lsl#18
98 eor $t0,$t0,$Elo,lsr#18
100 eor $t0,$t0,$Ehi,lsl#14
102 eor $t0,$t0,$Ehi,lsr#9
104 eor $t0,$t0,$Elo,lsl#23
106 adds $Tlo,$Tlo,$t0
107 ldr $t0,[sp,#$Foff+0] @ f.lo
115 eor $t0,$t0,$t2
[all …]
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| /arch/mips/include/asm/mach-malta/ |
| D | kernel-entry-init.h | 52 li t0, ((MIPS_SEGCFG_MK << MIPS_SEGCFG_AM_SHIFT) | \
58 or t0, t2
59 mtc0 t0, CP0_SEGCTL0
62 li t0, ((MIPS_SEGCFG_MUSUK << MIPS_SEGCFG_AM_SHIFT) | \
69 ins t0, t1, 16, 3
70 mtc0 t0, CP0_SEGCTL1
73 li t0, ((MIPS_SEGCFG_MUSUK << MIPS_SEGCFG_AM_SHIFT) | \
79 or t0, t2
80 mtc0 t0, CP0_SEGCTL2
83 mfc0 t0, $16, 5
[all …]
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| /arch/mips/alchemy/common/ |
| D | sleeper.S | 60 lw t0, 0(t1)
61 jalr t0
97 la t0, 1f
99 cache 0x14, 0(t0)
100 cache 0x14, 32(t0)
101 cache 0x14, 64(t0)
102 cache 0x14, 96(t0)
123 la t0, 1f
125 cache 0x14, 0(t0)
126 cache 0x14, 32(t0)
[all …]
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| /arch/mips/net/ |
| D | bpf_jit_asm.S | 48 slti t0, offset, 0; \
49 bgtz t0, bpf_slow_path_##TYPE##_neg; \
55 slt t0, $r_s0, offset; \
56 bgtz t0, bpf_slow_path_##TYPE; \
69 wsbh t0, $r_A
70 rotr $r_A, t0, 16
72 sll t0, $r_A, 24
75 or t0, t0, t1
78 or t0, t0, t2
80 or $r_A, t0, t1
[all …]
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| /arch/mips/include/asm/mach-paravirt/ |
| D | kernel-entry-init.h | 15 mfc0 t0, CP0_EBASE
16 andi t0, t0, 0x3ff # CPUNum
17 beqz t0, 1f
30 mfc0 t0, CP0_EBASE
31 andi t0, t0, 0x3ff # CPUNum
32 slti t1, t0, NR_CPUS
40 PTR_SLL t0, PTR_SCALESHIFT
41 PTR_ADDU t1, t1, t0
47 PTR_ADDU t1, t1, t0
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| /arch/mips/cavium-octeon/ |
| D | octeon-memcpy.S | 104 #undef t0
108 #define t0 $8 macro
192 EXC( LOAD t0, UNIT(0)(src), l_exc)
197 EXC( STORE t0, UNIT(0)(dst), s_exc_p16u)
201 EXC( LOAD t0, UNIT(4)(src), l_exc_copy)
205 EXC( STORE t0, UNIT(4)(dst), s_exc_p12u)
211 EXC( LOAD t0, UNIT(-8)(src), l_exc_copy_rewind16)
215 EXC( STORE t0, UNIT(-8)(dst), s_exc_p8u)
219 EXC( LOAD t0, UNIT(-4)(src), l_exc_copy_rewind16)
223 EXC( STORE t0, UNIT(-4)(dst), s_exc_p4u)
[all …]
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| /arch/ia64/lib/ |
| D | memcpy.S | 31 # define t0 r18 macro
53 or t0=in0,in1
56 or t0=t0,in2
77 and t0=0x7,t0
80 cmp.ne p6,p0=t0,r0
184 and t0=-8,src // t0 = src & ~7
187 ld8 t0=[t0] // t0 = 1st source word
197 shr.u t0=t0,t2
203 or t0=t0,t1
207 (p3) st1 [dst]=t0,1
[all …]
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| D | carta_random.S | 17 #define t0 r16 macro
24 pmpyshr2.u t0 = a, seed, 0
27 unpack2.l t0 = t1, t0
30 zxt4 lo = t0
31 shr.u hi = t0, 32
33 dep t0 = 0, hi, 15, 49 // t0 = (hi & 0x7fff)
35 shl t0 = t0, 16 // t0 = (hi & 0x7fff) << 16
38 add lo = lo, t0
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| /arch/mips/lib/ |
| D | csum_partial.S | 24 #undef t0
28 #define t0 $8 macro
119 lbu t0, (src)
122 sll t0, t0, 8
124 ADDC(sum, t0)
132 lhu t0, (src)
134 ADDC(sum, t0)
146 LOAD32 t0, 0x00(src)
148 ADDC(sum, t0)
157 ld t0, 0x00(src)
[all …]
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| D | memset.S | 34 #define FILLPTRG t0
95 sltiu t0, a2, STORSIZE /* very small region? */
96 bnez t0, .Lsmall_memset\@
97 andi t0, a0, STORMASK /* aligned? */
104 beqz t0, 1f
105 PTR_SUBU t0, STORSIZE /* alignment in bytes */
109 beqz t0, 1f
110 PTR_SUBU t0, AT /* alignment in bytes */
121 PTR_SUBU a0, t0 /* long align ptr */
122 PTR_ADDU a2, t0 /* correct size */
[all …]
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| /arch/alpha/lib/ |
| D | strchr.S | 22 ldq_u t0, 0(a0) # .. e1 : load first quadword
28 cmpbge zero, t0, t2 # .. e1 : bits set iff byte == zero
34 xor t0, a1, t1 # .. e1 : make bytes == c zero
36 or t2, t3, t0 # e1 : bits set iff char match or zero match
37 andnot t0, t4, t0 # e0 : clear garbage bits
38 bne t0, $found # .. e1 (zdb)
40 $loop: ldq t0, 8(v0) # e0 :
43 xor t0, a1, t1 # .. e1 (ev5 data stall)
44 cmpbge zero, t0, t2 # e0 : bits set iff byte == 0
46 or t2, t3, t0 # e0 :
[all …]
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| D | stxncpy.S | 58 mskql t0, a1, t0 # e0 : assemble the first output word
60 or t0, t3, t0 # e0 :
68 stq_u t0, 0(a0) # e0 :
70 ldq_u t0, 0(a1) # e0 :
73 cmpbge zero, t0, t8 # .. e1 (stall)
99 zapnot t0, t8, t0 # e0 : clear src bytes > null
101 or t0, t1, t0 # e1 :
103 1: stq_u t0, 0(a0) # e0 :
122 and a0, 7, t0 # .. e1 : find dest misalignment
124 addq a2, t0, a2 # .. e1 : bias count by dest misalignment
[all …]
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| D | ev67-strchr.S | 31 ldq_u t0, 0(a0) # L : load first quadword Latency=3
48 cmpbge zero, t0, t2 # E : bits set iff byte == zero
53 xor t0, a1, t1 # E : make bytes == c zero
55 or t2, t3, t0 # E : bits set iff char match or zero match
57 andnot t0, t4, t0 # E : clear garbage bits
58 cttz t0, a2 # U0 : speculative (in case we get a match)
60 bne t0, $found # U :
68 $loop: ldq t0, 8(v0) # L : Latency=3
70 xor t0, a1, t1 # E :
71 cmpbge zero, t0, t2 # E : bits set iff byte == 0
[all …]
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| /arch/x86/crypto/ |
| D | glue_helper-asm-avx2.S | 33 #define store_cbc_16way(src, dst, x0, x1, x2, x3, x4, x5, x6, x7, t0) \ argument
34 vpxor t0, t0, t0; \
35 vinserti128 $1, (src), t0, t0; \
36 vpxor t0, x0, x0; \
60 #define load_ctr_16way(iv, bswap, x0, x1, x2, x3, x4, x5, x6, x7, t0, t0x, t1, \ argument
62 vpcmpeqd t0, t0, t0; \
63 vpsrldq $8, t0, t0; /* ab: -1:0 ; cd: -1:0 */ \
64 vpaddq t0, t0, t4; /* ab: -2:0 ; cd: -2:0 */\
75 add2_le128(t2, t0, t4, t3, t5); /* ab: le2 ; cd: le3 */ \
77 add2_le128(t2, t0, t4, t3, t5); \
[all …]
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