| /drivers/gpu/drm/amd/powerplay/hwmgr/ |
| D | hardwaremanager.c | 35 bool phm_is_hw_access_blocked(struct pp_hwmgr *hwmgr) in phm_is_hw_access_blocked() argument
37 return hwmgr->block_hw_access; in phm_is_hw_access_blocked()
40 int phm_block_hw_access(struct pp_hwmgr *hwmgr, bool block) in phm_block_hw_access() argument
42 hwmgr->block_hw_access = block; in phm_block_hw_access()
46 int phm_setup_asic(struct pp_hwmgr *hwmgr) in phm_setup_asic() argument
48 PHM_FUNC_CHECK(hwmgr); in phm_setup_asic()
50 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, in phm_setup_asic()
52 if (NULL != hwmgr->hwmgr_func->asic_setup) in phm_setup_asic()
53 return hwmgr->hwmgr_func->asic_setup(hwmgr); in phm_setup_asic()
55 return phm_dispatch_table(hwmgr, &(hwmgr->setup_asic), in phm_setup_asic()
[all …]
|
| D | smu7_thermal.c | 29 int smu7_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr, in smu7_fan_ctrl_get_fan_speed_info() argument
32 if (hwmgr->thermal_controller.fanInfo.bNoFan) in smu7_fan_ctrl_get_fan_speed_info()
40 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, in smu7_fan_ctrl_get_fan_speed_info()
42 hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution) { in smu7_fan_ctrl_get_fan_speed_info()
45 fan_speed_info->min_rpm = hwmgr->thermal_controller.fanInfo.ulMinRPM; in smu7_fan_ctrl_get_fan_speed_info()
46 fan_speed_info->max_rpm = hwmgr->thermal_controller.fanInfo.ulMaxRPM; in smu7_fan_ctrl_get_fan_speed_info()
55 int smu7_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr, in smu7_fan_ctrl_get_fan_speed_percent() argument
62 if (hwmgr->thermal_controller.fanInfo.bNoFan) in smu7_fan_ctrl_get_fan_speed_percent()
65 duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, in smu7_fan_ctrl_get_fan_speed_percent()
67 duty = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, in smu7_fan_ctrl_get_fan_speed_percent()
[all …]
|
| D | hwmgr.c | 38 extern int cz_hwmgr_init(struct pp_hwmgr *hwmgr);
40 static int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr);
41 static void hwmgr_init_default_caps(struct pp_hwmgr *hwmgr);
42 static int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr);
43 static int fiji_set_asic_special_caps(struct pp_hwmgr *hwmgr);
44 static int tonga_set_asic_special_caps(struct pp_hwmgr *hwmgr);
45 static int topaz_set_asic_special_caps(struct pp_hwmgr *hwmgr);
54 struct pp_hwmgr *hwmgr; in hwmgr_init() local
59 hwmgr = kzalloc(sizeof(struct pp_hwmgr), GFP_KERNEL); in hwmgr_init()
60 if (hwmgr == NULL) in hwmgr_init()
[all …]
|
| D | smu7_clockpowergating.c | 28 static int smu7_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable) in smu7_enable_disable_uvd_dpm() argument
30 return smum_send_msg_to_smc(hwmgr->smumgr, enable ? in smu7_enable_disable_uvd_dpm()
35 static int smu7_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable) in smu7_enable_disable_vce_dpm() argument
37 return smum_send_msg_to_smc(hwmgr->smumgr, enable ? in smu7_enable_disable_vce_dpm()
42 static int smu7_enable_disable_samu_dpm(struct pp_hwmgr *hwmgr, bool enable) in smu7_enable_disable_samu_dpm() argument
44 return smum_send_msg_to_smc(hwmgr->smumgr, enable ? in smu7_enable_disable_samu_dpm()
49 static int smu7_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate) in smu7_update_uvd_dpm() argument
52 smum_update_smc_table(hwmgr, SMU_UVD_TABLE); in smu7_update_uvd_dpm()
53 return smu7_enable_disable_uvd_dpm(hwmgr, !bgate); in smu7_update_uvd_dpm()
56 static int smu7_update_vce_dpm(struct pp_hwmgr *hwmgr, bool bgate) in smu7_update_vce_dpm() argument
[all …]
|
| D | processpptables.c | 48 static uint16_t get_vce_table_offset(struct pp_hwmgr *hwmgr, in get_vce_table_offset() argument
72 static uint16_t get_vce_clock_info_array_offset(struct pp_hwmgr *hwmgr, in get_vce_clock_info_array_offset() argument
75 uint16_t table_offset = get_vce_table_offset(hwmgr, in get_vce_clock_info_array_offset()
84 static uint16_t get_vce_clock_info_array_size(struct pp_hwmgr *hwmgr, in get_vce_clock_info_array_size() argument
87 uint16_t table_offset = get_vce_clock_info_array_offset(hwmgr, in get_vce_clock_info_array_size()
100 static uint16_t get_vce_clock_voltage_limit_table_offset(struct pp_hwmgr *hwmgr, in get_vce_clock_voltage_limit_table_offset() argument
103 uint16_t table_offset = get_vce_clock_info_array_offset(hwmgr, in get_vce_clock_voltage_limit_table_offset()
107 return table_offset + get_vce_clock_info_array_size(hwmgr, in get_vce_clock_voltage_limit_table_offset()
113 static uint16_t get_vce_clock_voltage_limit_table_size(struct pp_hwmgr *hwmgr, in get_vce_clock_voltage_limit_table_size() argument
116 uint16_t table_offset = get_vce_clock_voltage_limit_table_offset(hwmgr, powerplay_table); in get_vce_clock_voltage_limit_table_size()
[all …]
|
| D | smu7_hwmgr.c | 118 int smu7_get_mc_microcode_version (struct pp_hwmgr *hwmgr) in smu7_get_mc_microcode_version() argument
120 cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 0x9F); in smu7_get_mc_microcode_version()
122 hwmgr->microcode_version_info.MC = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA); in smu7_get_mc_microcode_version()
127 uint16_t smu7_get_current_pcie_speed(struct pp_hwmgr *hwmgr) in smu7_get_current_pcie_speed() argument
132 speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE, in smu7_get_current_pcie_speed()
138 int smu7_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr) in smu7_get_current_pcie_lane_number() argument
143 link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE, in smu7_get_current_pcie_lane_number()
158 int smu7_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr) in smu7_enable_smc_voltage_controller() argument
160 if (hwmgr->feature_mask & PP_SMC_VOLTAGE_CONTROL_MASK) in smu7_enable_smc_voltage_controller()
161 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Voltage_Cntl_Enable); in smu7_enable_smc_voltage_controller()
[all …]
|
| D | cz_hwmgr.c | 69 uint32_t cz_get_eclk_level(struct pp_hwmgr *hwmgr, in cz_get_eclk_level() argument
74 hwmgr->dyn_state.vce_clock_voltage_dependency_table; in cz_get_eclk_level()
100 static uint32_t cz_get_sclk_level(struct pp_hwmgr *hwmgr, in cz_get_sclk_level() argument
105 hwmgr->dyn_state.vddc_dependency_on_sclk; in cz_get_sclk_level()
130 static uint32_t cz_get_uvd_level(struct pp_hwmgr *hwmgr, in cz_get_uvd_level() argument
135 hwmgr->dyn_state.uvd_clock_voltage_dependency_table; in cz_get_uvd_level()
161 static uint32_t cz_get_max_sclk_level(struct pp_hwmgr *hwmgr) in cz_get_max_sclk_level() argument
163 struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend); in cz_get_max_sclk_level()
166 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetMaxSclkLevel); in cz_get_max_sclk_level()
167 cz_hwmgr->max_sclk_level = smum_get_argument(hwmgr->smumgr) + 1; in cz_get_max_sclk_level()
[all …]
|
| D | cz_clockpowergating.c | 42 int cz_phm_set_asic_block_gating(struct pp_hwmgr *hwmgr, enum PHM_AsicBlock block, enum PHM_ClockGa… in cz_phm_set_asic_block_gating() argument
52 ret = cz_dpm_powerdown_uvd(hwmgr); in cz_phm_set_asic_block_gating()
54 ret = cz_dpm_powerup_uvd(hwmgr); in cz_phm_set_asic_block_gating()
65 bool cz_phm_is_safe_for_asic_block(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, e… in cz_phm_is_safe_for_asic_block() argument
71 int cz_phm_enable_disable_gfx_power_gating(struct pp_hwmgr *hwmgr, bool enable) in cz_phm_enable_disable_gfx_power_gating() argument
76 int cz_phm_smu_power_up_down_pcie(struct pp_hwmgr *hwmgr, uint32_t target, bool up, uint32_t args) in cz_phm_smu_power_up_down_pcie() argument
82 int cz_phm_initialize_display_phy_access(struct pp_hwmgr *hwmgr, bool initialize, bool accesshw) in cz_phm_initialize_display_phy_access() argument
88 int cz_phm_get_display_phy_access_info(struct pp_hwmgr *hwmgr) in cz_phm_get_display_phy_access_info() argument
94 int cz_phm_gate_unused_display_phys(struct pp_hwmgr *hwmgr) in cz_phm_gate_unused_display_phys() argument
100 int cz_phm_ungate_all_display_phys(struct pp_hwmgr *hwmgr) in cz_phm_ungate_all_display_phys() argument
[all …]
|
| D | process_pptables_v1_0.c | 40 static void set_hw_cap(struct pp_hwmgr *hwmgr, bool setIt, enum phm_platform_caps cap) in set_hw_cap() argument
43 phm_cap_set(hwmgr->platform_descriptor.platformCaps, cap); in set_hw_cap()
45 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, cap); in set_hw_cap()
55 static int set_platform_caps(struct pp_hwmgr *hwmgr, uint32_t powerplay_caps) in set_platform_caps() argument
69 hwmgr, in set_platform_caps()
75 hwmgr, in set_platform_caps()
81 hwmgr, in set_platform_caps()
87 hwmgr, in set_platform_caps()
93 hwmgr, in set_platform_caps()
99 hwmgr, in set_platform_caps()
[all …]
|
| D | smu7_powertune.c | 380 static int smu7_enable_didt(struct pp_hwmgr *hwmgr, const bool enable) in smu7_enable_didt() argument
387 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping)) { in smu7_enable_didt()
388 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_SQ_CTRL0); in smu7_enable_didt()
391 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_SQ_CTRL0, data); in smu7_enable_didt()
396 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRamping)) { in smu7_enable_didt()
397 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DB_CTRL0); in smu7_enable_didt()
400 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DB_CTRL0, data); in smu7_enable_didt()
405 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TDRamping)) { in smu7_enable_didt()
406 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TD_CTRL0); in smu7_enable_didt()
409 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TD_CTRL0, data); in smu7_enable_didt()
[all …]
|
| D | smu7_thermal.h | 41 extern int smu7_thermal_get_temperature(struct pp_hwmgr *hwmgr);
42 extern int smu7_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr);
43 extern int smu7_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr, struct phm_fan_speed_info *fan_…
44 extern int smu7_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr, uint32_t *speed);
45 extern int smu7_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr);
46 extern int smu7_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode);
47 extern int smu7_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr, uint32_t speed);
48 extern int smu7_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr);
49 extern int pp_smu7_thermal_initialize(struct pp_hwmgr *hwmgr);
50 extern int smu7_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmgr);
[all …]
|
| D | ppatomctrl.h | 282 extern bool atomctrl_get_pp_assign_pin(struct pp_hwmgr *hwmgr, const uint32_t pinId, pp_atomctrl_gp…
283 extern int atomctrl_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint32_t …
284 extern int atomctrl_get_voltage_evv(struct pp_hwmgr *hwmgr, uint16_t virtual_voltage_id, uint16_t *…
285 extern uint32_t atomctrl_get_mpll_reference_clock(struct pp_hwmgr *hwmgr);
286 extern int atomctrl_get_memory_clock_spread_spectrum(struct pp_hwmgr *hwmgr, const uint32_t memory_…
287 extern int atomctrl_get_engine_clock_spread_spectrum(struct pp_hwmgr *hwmgr, const uint32_t engine_…
288 extern int atomctrl_initialize_mc_reg_table(struct pp_hwmgr *hwmgr, uint8_t module_index, pp_atomct…
289 extern int atomctrl_set_engine_dram_timings_rv770(struct pp_hwmgr *hwmgr, uint32_t engine_clock, ui…
290 extern uint32_t atomctrl_get_reference_clock(struct pp_hwmgr *hwmgr);
291 extern int atomctrl_get_memory_pll_dividers_si(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_ato…
[all …]
|
| D | smu7_clockpowergating.h | 30 int smu7_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate);
31 int smu7_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate);
32 int smu7_powerdown_uvd(struct pp_hwmgr *hwmgr);
33 int smu7_powergate_samu(struct pp_hwmgr *hwmgr, bool bgate);
34 int smu7_powergate_acp(struct pp_hwmgr *hwmgr, bool bgate);
35 int smu7_disable_clock_power_gating(struct pp_hwmgr *hwmgr);
36 int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
38 int smu7_enable_per_cu_power_gating(struct pp_hwmgr *hwmgr, bool enable);
|
| /drivers/gpu/drm/amd/powerplay/ |
| D | amd_powerplay.c | 41 #define PP_CHECK_HW(hwmgr) \ argument
43 if ((hwmgr) == NULL || (hwmgr)->hwmgr_func == NULL) \
55 struct pp_hwmgr *hwmgr; in pp_sw_init() local
62 hwmgr = pp_handle->hwmgr; in pp_sw_init()
64 PP_CHECK_HW(hwmgr); in pp_sw_init()
66 if (hwmgr->pptable_func == NULL || in pp_sw_init()
67 hwmgr->pptable_func->pptable_init == NULL || in pp_sw_init()
68 hwmgr->hwmgr_func->backend_init == NULL) in pp_sw_init()
71 ret = hwmgr->pptable_func->pptable_init(hwmgr); in pp_sw_init()
75 ret = hwmgr->hwmgr_func->backend_init(hwmgr); in pp_sw_init()
[all …]
|
| /drivers/gpu/drm/amd/powerplay/smumgr/ |
| D | iceland_smc.c | 102 static void iceland_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr) in iceland_initialize_power_tune_defaults() argument
104 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); in iceland_initialize_power_tune_defaults()
110 cgs_query_system_info(hwmgr->device, &sys_info); in iceland_initialize_power_tune_defaults()
131 static int iceland_populate_svi_load_line(struct pp_hwmgr *hwmgr) in iceland_populate_svi_load_line() argument
133 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); in iceland_populate_svi_load_line()
144 static int iceland_populate_tdc_limit(struct pp_hwmgr *hwmgr) in iceland_populate_tdc_limit() argument
147 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); in iceland_populate_tdc_limit()
150 tdc_limit = (uint16_t)(hwmgr->dyn_state.cac_dtp_table->usTDC * 256); in iceland_populate_tdc_limit()
160 static int iceland_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset) in iceland_populate_dw8() argument
162 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); in iceland_populate_dw8()
[all …]
|
| D | polaris10_smc.c | 77 static int polaris10_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr, in polaris10_get_dependency_volt_by_clk() argument
83 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in polaris10_get_dependency_volt_by_clk()
149 static int polaris10_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr) in polaris10_populate_bapm_parameters_in_dpm_table() argument
151 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); in polaris10_populate_bapm_parameters_in_dpm_table()
156 (struct phm_ppt_v1_information *)(hwmgr->pptable); in polaris10_populate_bapm_parameters_in_dpm_table()
159 &hwmgr->thermal_controller.advanceFanControlParameters; in polaris10_populate_bapm_parameters_in_dpm_table()
197 static int polaris10_populate_svi_load_line(struct pp_hwmgr *hwmgr) in polaris10_populate_svi_load_line() argument
199 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); in polaris10_populate_svi_load_line()
210 static int polaris10_populate_tdc_limit(struct pp_hwmgr *hwmgr) in polaris10_populate_tdc_limit() argument
213 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); in polaris10_populate_tdc_limit()
[all …]
|
| D | fiji_smc.c | 84 static int fiji_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr, in fiji_get_dependency_volt_by_clk() argument
90 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in fiji_get_dependency_volt_by_clk()
199 static void fiji_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr) in fiji_initialize_power_tune_defaults() argument
201 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); in fiji_initialize_power_tune_defaults()
203 (struct phm_ppt_v1_information *)(hwmgr->pptable); in fiji_initialize_power_tune_defaults()
216 static int fiji_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr) in fiji_populate_bapm_parameters_in_dpm_table() argument
219 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); in fiji_populate_bapm_parameters_in_dpm_table()
225 (struct phm_ppt_v1_information *)(hwmgr->pptable); in fiji_populate_bapm_parameters_in_dpm_table()
228 &hwmgr->thermal_controller.advanceFanControlParameters; in fiji_populate_bapm_parameters_in_dpm_table()
300 static int fiji_populate_svi_load_line(struct pp_hwmgr *hwmgr) in fiji_populate_svi_load_line() argument
[all …]
|
| D | tonga_smc.c | 100 static int tonga_get_dependecy_volt_by_clk(struct pp_hwmgr *hwmgr, in tonga_get_dependecy_volt_by_clk() argument
105 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in tonga_get_dependecy_volt_by_clk()
107 (struct phm_ppt_v1_information *)(hwmgr->pptable); in tonga_get_dependecy_volt_by_clk()
164 static int tonga_populate_smc_vddc_table(struct pp_hwmgr *hwmgr, in tonga_populate_smc_vddc_table() argument
168 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in tonga_populate_smc_vddc_table()
188 static int tonga_populate_smc_vdd_gfx_table(struct pp_hwmgr *hwmgr, in tonga_populate_smc_vdd_gfx_table() argument
192 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in tonga_populate_smc_vdd_gfx_table()
212 static int tonga_populate_smc_vdd_ci_table(struct pp_hwmgr *hwmgr, in tonga_populate_smc_vdd_ci_table() argument
215 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); in tonga_populate_smc_vdd_ci_table()
249 static int tonga_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr, in tonga_populate_smc_mvdd_table() argument
[all …]
|
| D | smumgr.c | 89 int smum_thermal_avfs_enable(struct pp_hwmgr *hwmgr, in smum_thermal_avfs_enable() argument
92 if (NULL != hwmgr->smumgr->smumgr_funcs->thermal_avfs_enable) in smum_thermal_avfs_enable()
93 return hwmgr->smumgr->smumgr_funcs->thermal_avfs_enable(hwmgr); in smum_thermal_avfs_enable()
98 int smum_thermal_setup_fan_table(struct pp_hwmgr *hwmgr, in smum_thermal_setup_fan_table() argument
101 if (NULL != hwmgr->smumgr->smumgr_funcs->thermal_setup_fan_table) in smum_thermal_setup_fan_table()
102 return hwmgr->smumgr->smumgr_funcs->thermal_setup_fan_table(hwmgr); in smum_thermal_setup_fan_table()
107 int smum_update_sclk_threshold(struct pp_hwmgr *hwmgr) in smum_update_sclk_threshold() argument
110 if (NULL != hwmgr->smumgr->smumgr_funcs->update_sclk_threshold) in smum_update_sclk_threshold()
111 return hwmgr->smumgr->smumgr_funcs->update_sclk_threshold(hwmgr); in smum_update_sclk_threshold()
116 int smum_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type) in smum_update_smc_table() argument
[all …]
|
| D | polaris10_smc.h | 29 int polaris10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr);
30 int polaris10_populate_all_memory_levels(struct pp_hwmgr *hwmgr);
31 int polaris10_init_smc_table(struct pp_hwmgr *hwmgr);
32 int polaris10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr);
33 int polaris10_thermal_avfs_enable(struct pp_hwmgr *hwmgr);
34 int polaris10_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type);
35 int polaris10_update_sclk_threshold(struct pp_hwmgr *hwmgr);
38 int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr);
39 bool polaris10_is_dpm_running(struct pp_hwmgr *hwmgr);
|
| D | fiji_smc.h | 38 int fiji_populate_all_graphic_levels(struct pp_hwmgr *hwmgr);
39 int fiji_populate_all_memory_levels(struct pp_hwmgr *hwmgr);
40 int fiji_init_smc_table(struct pp_hwmgr *hwmgr);
41 int fiji_thermal_setup_fan_table(struct pp_hwmgr *hwmgr);
42 int fiji_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type);
43 int fiji_update_sclk_threshold(struct pp_hwmgr *hwmgr);
46 int fiji_process_firmware_header(struct pp_hwmgr *hwmgr);
47 int fiji_initialize_mc_reg_table(struct pp_hwmgr *hwmgr);
48 bool fiji_is_dpm_running(struct pp_hwmgr *hwmgr);
|
| /drivers/gpu/drm/amd/powerplay/eventmgr/ |
| D | psm.c | 29 struct pp_hwmgr *hwmgr = eventmgr->hwmgr; in psm_get_ui_state() local
32 table_entries = hwmgr->num_ps; in psm_get_ui_state()
33 state = hwmgr->ps; in psm_get_ui_state()
40 state = (struct pp_power_state *)((unsigned long)state + hwmgr->ps_size); in psm_get_ui_state()
49 struct pp_hwmgr *hwmgr = eventmgr->hwmgr; in psm_get_state_by_classification() local
52 table_entries = hwmgr->num_ps; in psm_get_state_by_classification()
53 state = hwmgr->ps; in psm_get_state_by_classification()
60 state = (struct pp_power_state *)((unsigned long)state + hwmgr->ps_size); in psm_get_state_by_classification()
69 struct pp_hwmgr *hwmgr = eventmgr->hwmgr; in psm_set_states() local
72 table_entries = hwmgr->num_ps; in psm_set_states()
[all …]
|
| D | eventtasks.c | 44 phm_force_dpm_levels(eventmgr->hwmgr, AMD_DPM_FORCED_LEVEL_AUTO); in pem_task_update_allowed_performance_levels()
52 struct pp_hwmgr *hwmgr; in pem_task_adjust_power_state() local
57 hwmgr = eventmgr->hwmgr; in pem_task_adjust_power_state()
59 hwmgr->request_ps = event_data->pnew_power_state; in pem_task_adjust_power_state()
71 return phm_power_down_asic(eventmgr->hwmgr); in pem_task_power_down_asic()
130 return phm_enable_dynamic_state_management(eventmgr->hwmgr); in pem_task_enable_dynamic_state_management()
135 return phm_disable_dynamic_state_management(eventmgr->hwmgr); in pem_task_disable_dynamic_state_management()
140 return phm_enable_clock_power_gatings(eventmgr->hwmgr); in pem_task_enable_clock_power_gatings_tasks()
145 return phm_powerdown_uvd(eventmgr->hwmgr); in pem_task_powerdown_uvd_tasks()
150 phm_powergate_uvd(eventmgr->hwmgr, true); in pem_task_powerdown_vce_tasks()
[all …]
|
| /drivers/gpu/drm/amd/powerplay/inc/ |
| D | hwmgr.h | 111 typedef int (*phm_table_function)(struct pp_hwmgr *hwmgr, void *input,
114 typedef bool (*phm_check_function)(struct pp_hwmgr *hwmgr);
214 extern int phm_dispatch_table(struct pp_hwmgr *hwmgr,
218 extern int phm_construct_table(struct pp_hwmgr *hwmgr,
222 extern int phm_destroy_table(struct pp_hwmgr *hwmgr,
289 int (*apply_state_adjust_rules)(struct pp_hwmgr *hwmgr,
301 int (*patch_boot_state)(struct pp_hwmgr *hwmgr,
304 int (*get_pp_table_entry)(struct pp_hwmgr *hwmgr,
306 int (*get_num_of_pp_table_entries)(struct pp_hwmgr *hwmgr);
307 int (*powerdown_uvd)(struct pp_hwmgr *hwmgr);
[all …]
|
| D | hardwaremanager.h | 337 extern int phm_enable_clock_power_gatings(struct pp_hwmgr *hwmgr);
338 extern int phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool gate);
339 extern int phm_powergate_vce(struct pp_hwmgr *hwmgr, bool gate);
340 extern int phm_powerdown_uvd(struct pp_hwmgr *hwmgr);
341 extern int phm_setup_asic(struct pp_hwmgr *hwmgr);
342 extern int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr);
343 extern int phm_disable_dynamic_state_management(struct pp_hwmgr *hwmgr);
344 extern bool phm_is_hw_access_blocked(struct pp_hwmgr *hwmgr);
345 extern int phm_block_hw_access(struct pp_hwmgr *hwmgr, bool block);
346 extern int phm_set_power_state(struct pp_hwmgr *hwmgr,
[all …]
|