| /drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_ih.c | 42 if (adev->irq.ih.ring_obj == NULL) { in amdgpu_ih_ring_alloc()
43 r = amdgpu_bo_create_kernel(adev, adev->irq.ih.ring_size, in amdgpu_ih_ring_alloc()
45 &adev->irq.ih.ring_obj, in amdgpu_ih_ring_alloc()
46 &adev->irq.ih.gpu_addr, in amdgpu_ih_ring_alloc()
47 (void **)&adev->irq.ih.ring); in amdgpu_ih_ring_alloc()
74 adev->irq.ih.ring_size = ring_size; in amdgpu_ih_ring_init()
75 adev->irq.ih.ptr_mask = adev->irq.ih.ring_size - 1; in amdgpu_ih_ring_init()
76 adev->irq.ih.rptr = 0; in amdgpu_ih_ring_init()
77 adev->irq.ih.use_bus_addr = use_bus_addr; in amdgpu_ih_ring_init()
79 if (adev->irq.ih.use_bus_addr) { in amdgpu_ih_ring_init()
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| D | tonga_ih.c | 65 adev->irq.ih.enabled = true; in tonga_ih_enable_interrupts()
85 adev->irq.ih.enabled = false; in tonga_ih_disable_interrupts()
86 adev->irq.ih.rptr = 0; in tonga_ih_disable_interrupts()
121 if (adev->irq.ih.use_bus_addr) in tonga_ih_irq_init()
122 WREG32(mmIH_RB_BASE, adev->irq.ih.rb_dma_addr >> 8); in tonga_ih_irq_init()
124 WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8); in tonga_ih_irq_init()
126 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in tonga_ih_irq_init()
139 if (adev->irq.ih.use_bus_addr) in tonga_ih_irq_init()
140 wptr_off = adev->irq.ih.rb_dma_addr + (adev->irq.ih.wptr_offs * 4); in tonga_ih_irq_init()
142 wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4); in tonga_ih_irq_init()
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| D | si_ih.c | 40 adev->irq.ih.enabled = true; in si_ih_enable_interrupts()
54 adev->irq.ih.enabled = false; in si_ih_disable_interrupts()
55 adev->irq.ih.rptr = 0; in si_ih_disable_interrupts()
65 WREG32(INTERRUPT_CNTL2, adev->irq.ih.gpu_addr >> 8); in si_ih_irq_init()
71 WREG32(IH_RB_BASE, adev->irq.ih.gpu_addr >> 8); in si_ih_irq_init()
72 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in si_ih_irq_init()
79 wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4); in si_ih_irq_init()
107 wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]); in si_ih_get_wptr()
112 wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask); in si_ih_get_wptr()
113 adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask; in si_ih_get_wptr()
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| D | cik_ih.c | 67 adev->irq.ih.enabled = true; in cik_ih_enable_interrupts()
89 adev->irq.ih.enabled = false; in cik_ih_disable_interrupts()
90 adev->irq.ih.rptr = 0; in cik_ih_disable_interrupts()
124 WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8); in cik_ih_irq_init()
125 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in cik_ih_irq_init()
134 wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4); in cik_ih_irq_init()
190 wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]); in cik_ih_get_wptr()
199 wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask); in cik_ih_get_wptr()
200 adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask; in cik_ih_get_wptr()
205 return (wptr & adev->irq.ih.ptr_mask); in cik_ih_get_wptr()
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| D | iceland_ih.c | 67 adev->irq.ih.enabled = true; in iceland_ih_enable_interrupts()
89 adev->irq.ih.enabled = false; in iceland_ih_disable_interrupts()
90 adev->irq.ih.rptr = 0; in iceland_ih_disable_interrupts()
125 WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8); in iceland_ih_irq_init()
127 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in iceland_ih_irq_init()
136 wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4); in iceland_ih_irq_init()
192 wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]); in iceland_ih_get_wptr()
201 wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask); in iceland_ih_get_wptr()
202 adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask; in iceland_ih_get_wptr()
207 return (wptr & adev->irq.ih.ptr_mask); in iceland_ih_get_wptr()
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| D | cz_ih.c | 67 adev->irq.ih.enabled = true; in cz_ih_enable_interrupts()
89 adev->irq.ih.enabled = false; in cz_ih_disable_interrupts()
90 adev->irq.ih.rptr = 0; in cz_ih_disable_interrupts()
125 WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8); in cz_ih_irq_init()
127 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in cz_ih_irq_init()
136 wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4); in cz_ih_irq_init()
192 wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]); in cz_ih_get_wptr()
201 wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask); in cz_ih_get_wptr()
202 adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask; in cz_ih_get_wptr()
207 return (wptr & adev->irq.ih.ptr_mask); in cz_ih_get_wptr()
[all …]
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| D | amdgpu_test.c | 51 if (adev->irq.ih.ring_obj) in amdgpu_do_test_moves()
52 n -= adev->irq.ih.ring_size; in amdgpu_do_test_moves()
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| D | amdgpu_irq.h | 67 struct amdgpu_ih_ring ih; member
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| /drivers/net/ethernet/sgi/ |
| D | ioc3-eth.c | 512 struct iphdr *ih; in ioc3_tcpudp_checksum() local
533 ih = (struct iphdr *) ((char *)eh + ETH_HLEN); in ioc3_tcpudp_checksum()
534 if (ip_is_fragment(ih)) in ioc3_tcpudp_checksum()
537 proto = ih->protocol; in ioc3_tcpudp_checksum()
543 (ih->tot_len - (ih->ihl << 2)) + in ioc3_tcpudp_checksum()
544 htons((uint16_t)ih->protocol) + in ioc3_tcpudp_checksum()
545 (ih->saddr >> 16) + (ih->saddr & 0xffff) + in ioc3_tcpudp_checksum()
546 (ih->daddr >> 16) + (ih->daddr & 0xffff); in ioc3_tcpudp_checksum()
1419 const struct iphdr *ih = ip_hdr(skb); in ioc3_start_xmit() local
1420 const int proto = ntohs(ih->protocol); in ioc3_start_xmit()
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| /drivers/gpu/drm/radeon/ |
| D | r600.c | 3319 rdev->ih.ring_obj = NULL; in r600_init()
3477 rdev->ih.ring_size = ring_size; in r600_ih_ring_init()
3478 rdev->ih.ptr_mask = rdev->ih.ring_size - 1; in r600_ih_ring_init()
3479 rdev->ih.rptr = 0; in r600_ih_ring_init()
3487 if (rdev->ih.ring_obj == NULL) { in r600_ih_ring_alloc()
3488 r = radeon_bo_create(rdev, rdev->ih.ring_size, in r600_ih_ring_alloc()
3491 NULL, NULL, &rdev->ih.ring_obj); in r600_ih_ring_alloc()
3496 r = radeon_bo_reserve(rdev->ih.ring_obj, false); in r600_ih_ring_alloc()
3499 r = radeon_bo_pin(rdev->ih.ring_obj, in r600_ih_ring_alloc()
3501 &rdev->ih.gpu_addr); in r600_ih_ring_alloc()
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| D | si.c | 5921 rdev->ih.enabled = true; in si_enable_interrupts()
5936 rdev->ih.enabled = false; in si_disable_interrupts()
5937 rdev->ih.rptr = 0; in si_disable_interrupts()
6022 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8); in si_irq_init()
6032 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8); in si_irq_init()
6033 rb_bufsz = order_base_2(rdev->ih.ring_size / 4); in si_irq_init()
6085 if (!rdev->ih.enabled) { in si_irq_set()
6417 wptr, rdev->ih.rptr, (wptr + 16) & rdev->ih.ptr_mask); in si_get_ih_wptr()
6418 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask; in si_get_ih_wptr()
6423 return (wptr & rdev->ih.ptr_mask); in si_get_ih_wptr()
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| D | cik.c | 6893 rdev->ih.enabled = true; in cik_enable_interrupts()
6915 rdev->ih.enabled = false; in cik_disable_interrupts()
6916 rdev->ih.rptr = 0; in cik_disable_interrupts()
7030 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8); in cik_irq_init()
7040 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8); in cik_irq_init()
7041 rb_bufsz = order_base_2(rdev->ih.ring_size / 4); in cik_irq_init()
7101 if (!rdev->ih.enabled) { in cik_irq_set()
7500 wptr, rdev->ih.rptr, (wptr + 16) & rdev->ih.ptr_mask); in cik_get_ih_wptr()
7501 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask; in cik_get_ih_wptr()
7506 return (wptr & rdev->ih.ptr_mask); in cik_get_ih_wptr()
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| D | evergreen.c | 4625 if (!rdev->ih.enabled) { in evergreen_irq_set()
5035 wptr, rdev->ih.rptr, (wptr + 16) & rdev->ih.ptr_mask); in evergreen_get_ih_wptr()
5036 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask; in evergreen_get_ih_wptr()
5041 return (wptr & rdev->ih.ptr_mask); in evergreen_get_ih_wptr()
5056 if (!rdev->ih.enabled || rdev->shutdown) in evergreen_irq_process()
5063 if (atomic_xchg(&rdev->ih.lock, 1)) in evergreen_irq_process()
5066 rptr = rdev->ih.rptr; in evergreen_irq_process()
5078 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff; in evergreen_irq_process()
5079 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff; in evergreen_irq_process()
5505 rptr &= rdev->ih.ptr_mask; in evergreen_irq_process()
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| /drivers/cpufreq/ |
| D | pmac64-cpufreq.c | 485 u64 max_freq, min_freq, ih, il; in g5_pm72_cpufreq_init() local
581 ih = *((u32 *)(eeprom + 0x10)); in g5_pm72_cpufreq_init()
585 if (il == ih) { in g5_pm72_cpufreq_init()
592 if (ih != 0 && il != 0) in g5_pm72_cpufreq_init()
593 min_freq = (max_freq * il) / ih; in g5_pm72_cpufreq_init()
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| /drivers/net/ethernet/tile/ |
| D | tilegx.c | 1725 struct iphdr *ih; in tso_headers_prepare() local
1747 ih = ip_hdr(skb); in tso_headers_prepare()
1749 isum_seed = ((0xFFFF - ih->check) + in tso_headers_prepare()
1750 (0xFFFF - ih->tot_len) + in tso_headers_prepare()
1751 (0xFFFF - ih->id)); in tso_headers_prepare()
1752 id = ntohs(ih->id); in tso_headers_prepare()
1778 ih = (struct iphdr *)(buf + ih_off); in tso_headers_prepare()
1779 ih->tot_len = htons(sh_len + p_len - ih_off); in tso_headers_prepare()
1780 ih->id = htons(id++); in tso_headers_prepare()
1781 ih->check = csum_long(isum_seed + ih->tot_len + in tso_headers_prepare()
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| D | tilepro.c | 1681 struct iphdr *ih = ip_hdr(skb); in tile_net_tx_tso() local
1682 unsigned int ih_len = ih->ihl * 4; in tile_net_tx_tso()
1744 BUG_ON(ih->protocol != IPPROTO_TCP); in tile_net_tx_tso()
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| /drivers/iommu/ |
| D | intel-svm.c | 159 unsigned long address, unsigned long pages, int ih, int gl) in intel_flush_svm_range_dev() argument
180 QI_EIOTLB_IH(ih) | QI_EIOTLB_AM(mask); in intel_flush_svm_range_dev()
205 unsigned long pages, int ih, int gl) in intel_flush_svm_range() argument
216 intel_flush_svm_range_dev(svm, sdev, address, pages, ih, gl); in intel_flush_svm_range()
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| D | dmar.c | 1315 int ih = 0; in qi_flush_iotlb() local
1325 desc.high = QI_IOTLB_ADDR(addr) | QI_IOTLB_IH(ih) in qi_flush_iotlb()
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| /drivers/net/ethernet/cavium/liquidio/ |
| D | octeon_iq.h | 184 u64 ih; member
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| /drivers/staging/wilc1000/ |
| D | linux_wlan.c | 980 struct iphdr *ih; in wilc_mac_xmit() local
1007 ih = (struct iphdr *)(skb->data + sizeof(struct ethhdr)); in wilc_mac_xmit()
1009 udp_buf = (char *)ih + sizeof(struct iphdr); in wilc_mac_xmit()
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| /drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/ |
| D | gpc.fuc | 138 mov $r1 #ih
325 ih:
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| D | hub.fuc | 84 mov $r1 #ih
309 ih:
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| /drivers/net/ethernet/packetengines/ |
| D | hamachi.c | 1519 struct iphdr *ih = (struct iphdr *) skb->data; in hamachi_rx() local
1524 if (ntohs(ih->tot_len) >= 46){ in hamachi_rx()
1526 if (!(ih->frag_off & cpu_to_be16(IP_MF|IP_OFFSET))) { in hamachi_rx()
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| /drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/ |
| D | g98.fuc0s | 103 mov $r1 #ih
134 ih:
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| /drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/ |
| D | com.fuc | 141 mov $r1 #ih
165 ih:
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