| /drivers/clk/imx/ |
| D | clk-pllv3.c | 112 unsigned long parent_rate) in clk_pllv3_recalc_rate() argument
117 return (div == 1) ? parent_rate * 22 : parent_rate * 20; in clk_pllv3_recalc_rate()
123 unsigned long parent_rate = *prate; in clk_pllv3_round_rate() local
125 return (rate >= parent_rate * 22) ? parent_rate * 22 : in clk_pllv3_round_rate()
126 parent_rate * 20; in clk_pllv3_round_rate()
130 unsigned long parent_rate) in clk_pllv3_set_rate() argument
135 if (rate == parent_rate * 22) in clk_pllv3_set_rate()
137 else if (rate == parent_rate * 20) in clk_pllv3_set_rate()
160 unsigned long parent_rate) in clk_pllv3_sys_recalc_rate() argument
165 return parent_rate * div / 2; in clk_pllv3_sys_recalc_rate()
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| /drivers/clk/at91/ |
| D | clk-h32mx.c | 34 unsigned long parent_rate) in clk_sama5d4_h32mx_recalc_rate() argument
41 return parent_rate / 2; in clk_sama5d4_h32mx_recalc_rate()
43 if (parent_rate > H32MX_MAX_FREQ) in clk_sama5d4_h32mx_recalc_rate()
45 return parent_rate; in clk_sama5d4_h32mx_recalc_rate()
49 unsigned long *parent_rate) in clk_sama5d4_h32mx_round_rate() argument
53 if (rate > *parent_rate) in clk_sama5d4_h32mx_round_rate()
54 return *parent_rate; in clk_sama5d4_h32mx_round_rate()
55 div = *parent_rate / 2; in clk_sama5d4_h32mx_round_rate()
59 if (rate - div < *parent_rate - rate) in clk_sama5d4_h32mx_round_rate()
62 return *parent_rate; in clk_sama5d4_h32mx_round_rate()
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| D | clk-plldiv.c | 28 unsigned long parent_rate) in clk_plldiv_recalc_rate() argument
36 return parent_rate / 2; in clk_plldiv_recalc_rate()
38 return parent_rate; in clk_plldiv_recalc_rate()
42 unsigned long *parent_rate) in clk_plldiv_round_rate() argument
46 if (rate > *parent_rate) in clk_plldiv_round_rate()
47 return *parent_rate; in clk_plldiv_round_rate()
48 div = *parent_rate / 2; in clk_plldiv_round_rate()
52 if (rate - div < *parent_rate - rate) in clk_plldiv_round_rate()
55 return *parent_rate; in clk_plldiv_round_rate()
59 unsigned long parent_rate) in clk_plldiv_set_rate() argument
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| D | clk-smd.c | 34 unsigned long parent_rate) in at91sam9x5_clk_smd_recalc_rate() argument
43 return parent_rate / (smddiv + 1); in at91sam9x5_clk_smd_recalc_rate()
47 unsigned long *parent_rate) in at91sam9x5_clk_smd_round_rate() argument
53 if (rate >= *parent_rate) in at91sam9x5_clk_smd_round_rate()
54 return *parent_rate; in at91sam9x5_clk_smd_round_rate()
56 div = *parent_rate / rate; in at91sam9x5_clk_smd_round_rate()
58 return *parent_rate / (SMD_MAX_DIV + 1); in at91sam9x5_clk_smd_round_rate()
60 bestrate = *parent_rate / div; in at91sam9x5_clk_smd_round_rate()
61 tmp = *parent_rate / (div + 1); in at91sam9x5_clk_smd_round_rate()
92 unsigned long parent_rate) in at91sam9x5_clk_smd_set_rate() argument
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| /drivers/clk/ |
| D | clk-multiplier.c | 19 unsigned long parent_rate) in __get_mult() argument
22 return DIV_ROUND_CLOSEST(rate, parent_rate); in __get_mult()
24 return rate / parent_rate; in __get_mult()
28 unsigned long parent_rate) in clk_multiplier_recalc_rate() argument
39 return parent_rate * val; in clk_multiplier_recalc_rate()
57 unsigned long parent_rate, current_rate, best_rate = ~0; in __bestmult() local
87 parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), in __bestmult()
89 current_rate = parent_rate * i; in __bestmult()
94 *best_parent_rate = parent_rate; in __bestmult()
102 unsigned long *parent_rate) in clk_multiplier_round_rate() argument
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| D | clk-cdce925.c | 69 static unsigned long cdce925_pll_calculate_rate(unsigned long parent_rate, in cdce925_pll_calculate_rate() argument
73 return parent_rate; /* In bypass mode runs at same frequency */ in cdce925_pll_calculate_rate()
74 return mult_frac(parent_rate, (unsigned long)n, (unsigned long)m); in cdce925_pll_calculate_rate()
78 unsigned long parent_rate) in cdce925_pll_recalc_rate() argument
83 return cdce925_pll_calculate_rate(parent_rate, data->n, data->m); in cdce925_pll_recalc_rate()
87 unsigned long parent_rate, u16 *n, u16 *m) in cdce925_pll_find_rate() argument
93 if (rate <= parent_rate) { in cdce925_pll_find_rate()
95 rate = parent_rate; in cdce925_pll_find_rate()
105 g = gcd(rate, parent_rate); in cdce925_pll_find_rate()
106 um = parent_rate / g; in cdce925_pll_find_rate()
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| D | clk-vt8500.c | 124 unsigned long parent_rate) in vt8500_dclk_recalc_rate() argument
137 return parent_rate / div; in vt8500_dclk_recalc_rate()
167 unsigned long parent_rate) in vt8500_dclk_set_rate() argument
176 divisor = parent_rate / rate; in vt8500_dclk_set_rate()
359 static int vt8500_find_pll_bits(unsigned long rate, unsigned long parent_rate, in vt8500_find_pll_bits() argument
365 if ((rate < parent_rate * 4) || (rate > parent_rate * 62)) { in vt8500_find_pll_bits()
371 if (rate <= parent_rate * 31) in vt8500_find_pll_bits()
377 *multiplier = rate / (parent_rate / *prediv); in vt8500_find_pll_bits()
378 tclk = (parent_rate / *prediv) * *multiplier; in vt8500_find_pll_bits()
399 unsigned long parent_rate, u32 *multiplier, u32 *divisor1, in wm8650_find_pll_bits() argument
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| D | clk-xgene.c | 86 unsigned long parent_rate) in xgene_clk_pll_recalc_rate() argument
105 fvco = parent_rate * (N_DIV_RD(pll) + 4); in xgene_clk_pll_recalc_rate()
115 fref = parent_rate / nref; in xgene_clk_pll_recalc_rate()
124 fvco = parent_rate * SC_N_DIV_RD(pll); in xgene_clk_pll_recalc_rate()
127 clk_hw_get_name(hw), fvco / nout, parent_rate, in xgene_clk_pll_recalc_rate()
255 unsigned long parent_rate) in xgene_clk_pmd_recalc_rate() argument
274 ret = (u64)parent_rate; in xgene_clk_pmd_recalc_rate()
286 ret = (u64)parent_rate; in xgene_clk_pmd_recalc_rate()
292 unsigned long *parent_rate) in xgene_clk_pmd_round_rate() argument
297 if (!rate || rate >= *parent_rate) in xgene_clk_pmd_round_rate()
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| D | clk-highbank.c | 106 unsigned long parent_rate) in clk_pll_recalc_rate() argument
113 return parent_rate; in clk_pll_recalc_rate()
117 vco_freq = parent_rate * (divf + 1); in clk_pll_recalc_rate()
147 unsigned long *parent_rate) in clk_pll_round_rate() argument
150 unsigned long ref_freq = *parent_rate; in clk_pll_round_rate()
158 unsigned long parent_rate) in clk_pll_set_rate() argument
164 clk_pll_calc(rate, parent_rate, &divq, &divf); in clk_pll_set_rate()
206 unsigned long parent_rate) in clk_cpu_periphclk_recalc_rate() argument
210 return parent_rate / div; in clk_cpu_periphclk_recalc_rate()
218 unsigned long parent_rate) in clk_cpu_a9bclk_recalc_rate() argument
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| D | clk-divider.c | 118 unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate, in divider_recalc_rate() argument
131 return parent_rate; in divider_recalc_rate()
134 return DIV_ROUND_UP_ULL((u64)parent_rate, div); in divider_recalc_rate()
139 unsigned long parent_rate) in clk_divider_recalc_rate() argument
147 return divider_recalc_rate(hw, parent_rate, val, divider->table, in clk_divider_recalc_rate()
209 unsigned long parent_rate, unsigned long rate, in _div_round_up() argument
212 int div = DIV_ROUND_UP_ULL((u64)parent_rate, rate); in _div_round_up()
223 unsigned long parent_rate, unsigned long rate, in _div_round_closest() argument
229 up = DIV_ROUND_UP_ULL((u64)parent_rate, rate); in _div_round_closest()
230 down = parent_rate / rate; in _div_round_closest()
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| D | clk-fractional-divider.c | 20 unsigned long parent_rate) in clk_fd_recalc_rate() argument
44 return parent_rate; in clk_fd_recalc_rate()
46 ret = (u64)parent_rate * m; in clk_fd_recalc_rate()
53 unsigned long *parent_rate) in clk_fd_round_rate() argument
60 if (!rate || rate >= *parent_rate) in clk_fd_round_rate()
61 return *parent_rate; in clk_fd_round_rate()
68 scale = fls_long(*parent_rate / rate - 1); in clk_fd_round_rate()
72 rational_best_approximation(rate, *parent_rate, in clk_fd_round_rate()
76 ret = (u64)*parent_rate * m; in clk_fd_round_rate()
83 unsigned long parent_rate) in clk_fd_set_rate() argument
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| D | clk-si5351.c | 270 unsigned long parent_rate) in si5351_clkin_recalc_rate() argument
277 rate = parent_rate; in si5351_clkin_recalc_rate()
278 if (parent_rate > 160000000) { in si5351_clkin_recalc_rate()
281 } else if (parent_rate > 80000000) { in si5351_clkin_recalc_rate()
284 } else if (parent_rate > 40000000) { in si5351_clkin_recalc_rate()
325 unsigned long parent_rate) in si5351_vxco_recalc_rate() argument
419 unsigned long parent_rate) in si5351_pll_recalc_rate() argument
431 return parent_rate; in si5351_pll_recalc_rate()
437 rate *= parent_rate; in si5351_pll_recalc_rate()
444 parent_rate, (unsigned long)rate); in si5351_pll_recalc_rate()
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| /drivers/clk/pxa/ |
| D | clk-pxa27x.c | 149 unsigned long parent_rate) in clk_pxa27x_cpll_get_rate() argument
162 L = l * parent_rate; in clk_pxa27x_cpll_get_rate()
171 unsigned long parent_rate) in clk_pxa27x_lcd_base_get_rate() argument
181 return parent_rate * 2; in clk_pxa27x_lcd_base_get_rate()
183 return parent_rate; in clk_pxa27x_lcd_base_get_rate()
187 return parent_rate; in clk_pxa27x_lcd_base_get_rate()
189 return parent_rate / 2; in clk_pxa27x_lcd_base_get_rate()
190 return parent_rate / 4; in clk_pxa27x_lcd_base_get_rate()
221 unsigned long parent_rate) in clk_pxa27x_core_get_rate() argument
234 return parent_rate; in clk_pxa27x_core_get_rate()
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| D | clk-pxa3xx.c | 85 unsigned long parent_rate) in clk_pxa3xx_ac97_get_rate() argument
94 rate = parent_rate / 2; in clk_pxa3xx_ac97_get_rate()
104 unsigned long parent_rate) in clk_pxa3xx_smemc_get_rate() argument
109 return (parent_rate / 48) * smcfs_mult[(acsr >> 23) & 0x7] / in clk_pxa3xx_smemc_get_rate()
195 unsigned long parent_rate) in clk_pxa3xx_system_bus_get_rate() argument
201 return parent_rate; in clk_pxa3xx_system_bus_get_rate()
202 return parent_rate / 48 * hss_mult[hss]; in clk_pxa3xx_system_bus_get_rate()
217 unsigned long parent_rate) in clk_pxa3xx_core_get_rate() argument
219 return parent_rate; in clk_pxa3xx_core_get_rate()
242 unsigned long parent_rate) in clk_pxa3xx_run_get_rate() argument
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| /drivers/clk/microchip/ |
| D | clk-core.c | 127 unsigned long parent_rate, in calc_best_divided_rate() argument
138 div = parent_rate / rate; in calc_best_divided_rate()
142 divided_rate = parent_rate / div; in calc_best_divided_rate()
143 divided_rate_down = parent_rate / div_up; in calc_best_divided_rate()
158 unsigned long parent_rate) in pbclk_recalc_rate() argument
162 return parent_rate / pbclk_read_pbdiv(pb); in pbclk_recalc_rate()
166 unsigned long *parent_rate) in pbclk_round_rate() argument
168 return calc_best_divided_rate(rate, *parent_rate, in pbclk_round_rate()
173 unsigned long parent_rate) in pbclk_set_rate() argument
187 div = DIV_ROUND_CLOSEST(parent_rate, rate); in pbclk_set_rate()
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| /drivers/clk/sunxi/ |
| D | clk-sun9i-cpus.c | 51 unsigned long parent_rate) in sun9i_a80_cpus_clk_recalc_rate() argument
62 parent_rate /= SUN9I_CPUS_PLL4_DIV_GET(reg) + 1; in sun9i_a80_cpus_clk_recalc_rate()
65 rate = parent_rate / (SUN9I_CPUS_DIV_GET(reg) + 1); in sun9i_a80_cpus_clk_recalc_rate()
71 u8 parent, unsigned long parent_rate) in sun9i_a80_cpus_clk_round() argument
79 if (parent_rate && rate > parent_rate) in sun9i_a80_cpus_clk_round()
80 rate = parent_rate; in sun9i_a80_cpus_clk_round()
82 div = DIV_ROUND_UP(parent_rate, rate); in sun9i_a80_cpus_clk_round()
108 return parent_rate / pre_div / div; in sun9i_a80_cpus_clk_round()
116 unsigned long parent_rate, best = 0, child_rate, best_child_rate = 0; in sun9i_a80_cpus_clk_determine_rate() local
126 parent_rate = clk_hw_round_rate(parent, rate); in sun9i_a80_cpus_clk_determine_rate()
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| D | clk-sun9i-core.c | 113 if (req->parent_rate < req->rate) in sun9i_a80_get_gt_factors()
114 req->rate = req->parent_rate; in sun9i_a80_get_gt_factors()
116 div = DIV_ROUND_UP(req->parent_rate, req->rate); in sun9i_a80_get_gt_factors()
122 req->rate = req->parent_rate / div; in sun9i_a80_get_gt_factors()
172 if (req->parent_rate < req->rate) in sun9i_a80_get_ahb_factors()
173 req->rate = req->parent_rate; in sun9i_a80_get_ahb_factors()
175 _p = order_base_2(DIV_ROUND_UP(req->parent_rate, req->rate)); in sun9i_a80_get_ahb_factors()
181 req->rate = req->parent_rate >> _p; in sun9i_a80_get_ahb_factors()
252 if (req->parent_rate < req->rate) in sun9i_a80_get_apb1_factors()
253 req->rate = req->parent_rate; in sun9i_a80_get_apb1_factors()
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| D | clk-sunxi.c | 95 u32 parent_freq_mhz = req->parent_rate / 1000000; in sun6i_a31_get_pll1_factors()
214 div = req->rate / req->parent_rate; in sun4i_get_pll5_factors()
215 req->rate = req->parent_rate * div; in sun4i_get_pll5_factors()
241 div = req->rate / req->parent_rate; in sun6i_a31_get_pll6_factors()
242 req->rate = req->parent_rate * div; in sun6i_a31_get_pll6_factors()
262 if (req->parent_rate < req->rate) in sun5i_a13_get_ahb_factors()
263 req->rate = req->parent_rate; in sun5i_a13_get_ahb_factors()
274 div = order_base_2(DIV_ROUND_UP(req->parent_rate, req->rate)); in sun5i_a13_get_ahb_factors()
280 req->rate = req->parent_rate >> div; in sun5i_a13_get_ahb_factors()
304 if (req->parent_rate && req->rate > req->parent_rate) in sun6i_get_ahb1_factors()
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| /drivers/clk/bcm/ |
| D | clk-iproc-asiu.c | 79 unsigned long parent_rate) in iproc_asiu_clk_recalc_rate() argument
86 if (parent_rate == 0) { in iproc_asiu_clk_recalc_rate()
94 clk->rate = parent_rate; in iproc_asiu_clk_recalc_rate()
95 return parent_rate; in iproc_asiu_clk_recalc_rate()
104 clk->rate = parent_rate / (div_h + div_l); in iproc_asiu_clk_recalc_rate()
106 __func__, clk->rate, parent_rate, div_h, div_l); in iproc_asiu_clk_recalc_rate()
112 unsigned long *parent_rate) in iproc_asiu_clk_round_rate() argument
116 if (rate == 0 || *parent_rate == 0) in iproc_asiu_clk_round_rate()
119 if (rate == *parent_rate) in iproc_asiu_clk_round_rate()
120 return *parent_rate; in iproc_asiu_clk_round_rate()
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| /drivers/clk/ti/ |
| D | fapll.c | 167 unsigned long parent_rate) in ti_fapll_recalc_rate() argument
174 return parent_rate; in ti_fapll_recalc_rate()
176 rate = parent_rate; in ti_fapll_recalc_rate()
201 unsigned long parent_rate, in ti_fapll_set_div_mult() argument
210 if (rate < parent_rate) { in ti_fapll_set_div_mult()
215 *mult_n = rate / parent_rate; in ti_fapll_set_div_mult()
224 unsigned long *parent_rate) in ti_fapll_round_rate() argument
232 error = ti_fapll_set_div_mult(rate, *parent_rate, in ti_fapll_round_rate()
237 rate = *parent_rate / pre_div_p; in ti_fapll_round_rate()
244 unsigned long parent_rate) in ti_fapll_set_rate() argument
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| /drivers/clk/qcom/ |
| D | clk-rcg2.c | 153 clk_rcg2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) in clk_rcg2_recalc_rate() argument
176 return calc_rate(parent_rate, m, n, mode, hid_div); in clk_rcg2_recalc_rate()
281 unsigned long parent_rate) in clk_rcg2_set_rate() argument
287 unsigned long rate, unsigned long parent_rate, u8 index) in clk_rcg2_set_rate_and_parent() argument
336 unsigned long parent_rate) in clk_rcg2_shared_set_rate() argument
350 clk_rcg2_shared_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) in clk_rcg2_shared_recalc_rate() argument
354 return rcg->current_freq = clk_rcg2_recalc_rate(hw, parent_rate); in clk_rcg2_shared_recalc_rate()
410 unsigned long parent_rate) in clk_edp_pixel_set_rate() argument
416 s64 src_rate = parent_rate; in clk_edp_pixel_set_rate()
449 unsigned long rate, unsigned long parent_rate, u8 index) in clk_edp_pixel_set_rate_and_parent() argument
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| /drivers/clk/sunxi-ng/ |
| D | ccu_phase.c | 20 unsigned int parent_rate, grandparent_rate; in ccu_phase_get_phase() local
38 parent_rate = clk_hw_get_rate(parent); in ccu_phase_get_phase()
39 if (!parent_rate) in ccu_phase_get_phase()
53 parent_div = grandparent_rate / parent_rate; in ccu_phase_get_phase()
63 unsigned int parent_rate, grandparent_rate; in ccu_phase_set_phase() local
74 parent_rate = clk_hw_get_rate(parent); in ccu_phase_set_phase()
75 if (!parent_rate) in ccu_phase_set_phase()
92 parent_div = grandparent_rate / parent_rate; in ccu_phase_set_phase()
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| D | ccu_mult.c | 23 unsigned long parent_rate, in ccu_mult_round_rate() argument
30 ccu_mult_find_best(parent_rate, rate, 1 << cm->mult.width, &n); in ccu_mult_round_rate()
32 return parent_rate * n; in ccu_mult_round_rate()
57 unsigned long parent_rate) in ccu_mult_recalc_rate() argument
68 &parent_rate); in ccu_mult_recalc_rate()
70 return parent_rate * (val + 1); in ccu_mult_recalc_rate()
83 unsigned long parent_rate) in ccu_mult_set_rate() argument
91 &parent_rate); in ccu_mult_set_rate()
93 ccu_mult_find_best(parent_rate, rate, 1 << cm->mult.width, &n); in ccu_mult_set_rate()
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| /drivers/clk/mxs/ |
| D | clk-frac.c | 40 unsigned long parent_rate) in clk_frac_recalc_rate() argument
49 tmp_rate = (u64)parent_rate * div; in clk_frac_recalc_rate()
57 unsigned long parent_rate = *prate; in clk_frac_round_rate() local
61 if (rate > parent_rate) in clk_frac_round_rate()
66 do_div(tmp, parent_rate); in clk_frac_round_rate()
72 tmp_rate = (u64)parent_rate * div; in clk_frac_round_rate()
80 unsigned long parent_rate) in clk_frac_set_rate() argument
87 if (rate > parent_rate) in clk_frac_set_rate()
92 do_div(tmp, parent_rate); in clk_frac_set_rate()
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| /drivers/clk/tegra/ |
| D | clk-pll.c | 494 unsigned long rate, unsigned long parent_rate) in _get_table_rate() argument
501 if (sel->input_rate == parent_rate && in _get_table_rate()
528 unsigned long rate, unsigned long parent_rate) in _calc_rate() argument
535 switch (parent_rate) { in _calc_rate()
552 cfreq = parent_rate / (parent_rate / 1000000); in _calc_rate()
556 __func__, parent_rate); in _calc_rate()
565 cfg->m = parent_rate / cfreq; in _calc_rate()
780 unsigned long parent_rate) in clk_pll_set_rate() argument
797 if (_get_table_rate(hw, &cfg, rate, parent_rate) && in clk_pll_set_rate()
798 pll->params->calc_rate(hw, &cfg, rate, parent_rate)) { in clk_pll_set_rate()
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