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Searched refs:regval (Results 1 – 25 of 162) sorted by relevance

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/drivers/media/pci/cx23885/
Dcx23885-417.c284 u32 regval; in cx23885_mc417_init() local
289 regval = MC417_SPD_CTL(MC417_SPD_CTL_FAST) | in cx23885_mc417_init()
292 cx_write(MC417_CTL, regval); in cx23885_mc417_init()
295 regval = MC417_MIRDY; in cx23885_mc417_init()
296 cx_write(MC417_OEN, regval); in cx23885_mc417_init()
299 regval = MC417_MIWR | MC417_MIRD | MC417_MICS; in cx23885_mc417_init()
300 cx_write(MC417_RWD, regval); in cx23885_mc417_init()
320 u32 regval; in mc417_register_write() local
328 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE0 | in mc417_register_write()
330 cx_write(MC417_RWD, regval); in mc417_register_write()
[all …]
/drivers/rapidio/switches/
Dtsi57x.c124 u32 regval; in tsi57x_set_domain() local
132 TSI578_SP_MODE_GLBL, &regval); in tsi57x_set_domain()
134 regval & ~TSI578_SP_MODE_LUT_512); in tsi57x_set_domain()
146 u32 regval; in tsi57x_get_domain() local
152 TSI578_GLBL_ROUTE_BASE, &regval); in tsi57x_get_domain()
154 *sw_domain = (u8)(regval >> 24); in tsi57x_get_domain()
162 u32 regval; in tsi57x_em_init() local
171 TSI578_SP_MODE(portnum), &regval); in tsi57x_em_init()
174 regval & ~TSI578_SP_MODE_PW_DIS); in tsi57x_em_init()
179 &regval); in tsi57x_em_init()
[all …]
Didt_gen2.c203 u32 regval; in idtg2_get_domain() local
209 IDT_RIO_DOMAIN, &regval); in idtg2_get_domain()
211 *sw_domain = (u8)(regval & 0xff); in idtg2_get_domain()
219 u32 regval; in idtg2_em_init() local
244 rio_read_config_32(rdev, IDT_DEV_CTRL_1, &regval); in idtg2_em_init()
246 regval | IDT_DEV_CTRL_1_GENPW | IDT_DEV_CTRL_1_PRSTBEH); in idtg2_em_init()
262 rio_read_config_32(rdev, IDT_PORT_OPS(i), &regval); in idtg2_em_init()
264 IDT_PORT_OPS(i), regval | IDT_PORT_OPS_GENPW | in idtg2_em_init()
284 rio_read_config_32(rdev, IDT_LANE_CTRL(i), &regval); in idtg2_em_init()
286 regval | IDT_LANE_CTRL_GENPW); in idtg2_em_init()
[all …]
/drivers/watchdog/
Dts72xx_wdt.c52 int regval; member
88 int regval; member
113 return ts72xx_wdt_map[i].regval; in timeout_to_regval()
126 static int regval_to_timeout(int regval) in regval_to_timeout() argument
131 if (ts72xx_wdt_map[i].regval == regval) in regval_to_timeout()
166 __raw_writeb((u8)wdt->regval, wdt->control_reg); in ts72xx_wdt_start()
184 int regval; in ts72xx_wdt_open() local
190 regval = timeout_to_regval(timeout); in ts72xx_wdt_open()
191 if (regval < 0) { in ts72xx_wdt_open()
195 return regval; in ts72xx_wdt_open()
[all …]
Dmax77620_wdt.c60 u8 regval; in max77620_wdt_set_timeout() local
65 regval = MAX77620_TWD_2s; in max77620_wdt_set_timeout()
70 regval = MAX77620_TWD_16s; in max77620_wdt_set_timeout()
75 regval = MAX77620_TWD_64s; in max77620_wdt_set_timeout()
80 regval = MAX77620_TWD_128s; in max77620_wdt_set_timeout()
91 MAX77620_TWD_MASK, regval); in max77620_wdt_set_timeout()
116 unsigned int regval; in max77620_wdt_probe() local
158 ret = regmap_read(wdt->rmap, MAX77620_REG_CNFGGLBL2, &regval); in max77620_wdt_probe()
164 switch (regval & MAX77620_TWD_MASK) { in max77620_wdt_probe()
179 if (regval & MAX77620_WDTEN) in max77620_wdt_probe()
/drivers/phy/
Dphy-berlin-sata.c71 u32 regval; in phy_berlin_sata_reg_setbits() local
77 regval = readl(ctrl_reg + PORT_VSR_DATA); in phy_berlin_sata_reg_setbits()
78 regval &= ~mask; in phy_berlin_sata_reg_setbits()
79 regval |= val; in phy_berlin_sata_reg_setbits()
80 writel(regval, ctrl_reg + PORT_VSR_DATA); in phy_berlin_sata_reg_setbits()
89 u32 regval; in phy_berlin_sata_power_on() local
97 regval = readl(priv->base + HOST_VSA_DATA); in phy_berlin_sata_power_on()
98 regval &= ~desc->power_bit; in phy_berlin_sata_power_on()
99 writel(regval, priv->base + HOST_VSA_DATA); in phy_berlin_sata_power_on()
103 regval = readl(priv->base + HOST_VSA_DATA); in phy_berlin_sata_power_on()
[all …]
/drivers/regulator/
Dab3100.c163 u8 regval; in ab3100_enable_regulator() local
166 &regval); in ab3100_enable_regulator()
174 if (regval & AB3100_REG_ON_MASK) in ab3100_enable_regulator()
177 regval |= AB3100_REG_ON_MASK; in ab3100_enable_regulator()
180 regval); in ab3100_enable_regulator()
194 u8 regval; in ab3100_disable_regulator() local
212 &regval); in ab3100_disable_regulator()
218 regval &= ~AB3100_REG_ON_MASK; in ab3100_disable_regulator()
220 regval); in ab3100_disable_regulator()
226 u8 regval; in ab3100_is_enabled_regulator() local
[all …]
Dlp8755.c96 unsigned int regval; in lp8755_buck_enable_time() local
100 ret = lp8755_read(pchip, 0x12 + id, &regval); in lp8755_buck_enable_time()
105 return (regval & 0xff) * 100; in lp8755_buck_enable_time()
154 unsigned int regval; in lp8755_buck_get_mode() local
158 ret = lp8755_read(pchip, 0x06, &regval); in lp8755_buck_get_mode()
163 if (regval & (0x01 << id)) in lp8755_buck_get_mode()
166 ret = lp8755_read(pchip, 0x08 + id, &regval); in lp8755_buck_get_mode()
171 if (regval & 0x20) in lp8755_buck_get_mode()
185 unsigned int regval = 0x00; in lp8755_buck_set_ramp() local
192 regval = 0x07; in lp8755_buck_set_ramp()
[all …]
Dab8500-ext.c513 u8 regval; in ab8500_ext_regulator_enable() local
525 regval = info->update_val_hp; in ab8500_ext_regulator_enable()
527 regval = info->update_val; in ab8500_ext_regulator_enable()
531 info->update_mask, regval); in ab8500_ext_regulator_enable()
541 info->update_mask, regval); in ab8500_ext_regulator_enable()
550 u8 regval; in ab8500_ext_regulator_disable() local
561 regval = info->update_val_hw; in ab8500_ext_regulator_disable()
563 regval = 0; in ab8500_ext_regulator_disable()
567 info->update_mask, regval); in ab8500_ext_regulator_disable()
577 info->update_mask, regval); in ab8500_ext_regulator_disable()
[all …]
/drivers/net/wireless/ath/ath9k/
Dar9002_phy.c380 u32 regval; in ar9002_hw_antdiv_comb_conf_get() local
382 regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); in ar9002_hw_antdiv_comb_conf_get()
383 antconf->main_lna_conf = (regval & AR_PHY_9285_ANT_DIV_MAIN_LNACONF) >> in ar9002_hw_antdiv_comb_conf_get()
385 antconf->alt_lna_conf = (regval & AR_PHY_9285_ANT_DIV_ALT_LNACONF) >> in ar9002_hw_antdiv_comb_conf_get()
387 antconf->fast_div_bias = (regval & AR_PHY_9285_FAST_DIV_BIAS) >> in ar9002_hw_antdiv_comb_conf_get()
397 u32 regval; in ar9002_hw_antdiv_comb_conf_set() local
399 regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); in ar9002_hw_antdiv_comb_conf_set()
400 regval &= ~(AR_PHY_9285_ANT_DIV_MAIN_LNACONF | in ar9002_hw_antdiv_comb_conf_set()
403 regval |= ((antconf->main_lna_conf << AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S) in ar9002_hw_antdiv_comb_conf_set()
405 regval |= ((antconf->alt_lna_conf << AR_PHY_9285_ANT_DIV_ALT_LNACONF_S) in ar9002_hw_antdiv_comb_conf_set()
[all …]
Dar9003_phy.c1528 u32 regval; in ar9003_hw_antdiv_comb_conf_get() local
1530 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); in ar9003_hw_antdiv_comb_conf_get()
1531 antconf->main_lna_conf = (regval & AR_PHY_ANT_DIV_MAIN_LNACONF) >> in ar9003_hw_antdiv_comb_conf_get()
1533 antconf->alt_lna_conf = (regval & AR_PHY_ANT_DIV_ALT_LNACONF) >> in ar9003_hw_antdiv_comb_conf_get()
1535 antconf->fast_div_bias = (regval & AR_PHY_ANT_FAST_DIV_BIAS) >> in ar9003_hw_antdiv_comb_conf_get()
1560 u32 regval; in ar9003_hw_antdiv_comb_conf_set() local
1562 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); in ar9003_hw_antdiv_comb_conf_set()
1563 regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF | in ar9003_hw_antdiv_comb_conf_set()
1568 regval |= ((antconf->main_lna_conf << AR_PHY_ANT_DIV_MAIN_LNACONF_S) in ar9003_hw_antdiv_comb_conf_set()
1570 regval |= ((antconf->alt_lna_conf << AR_PHY_ANT_DIV_ALT_LNACONF_S) in ar9003_hw_antdiv_comb_conf_set()
[all …]
/drivers/edac/
Dsynopsys_edac.c156 u32 regval, clearval = 0; in synps_edac_geterror_info() local
158 regval = readl(base + STAT_OFST); in synps_edac_geterror_info()
159 if (!regval) in synps_edac_geterror_info()
162 p->ce_cnt = (regval & STAT_CECNT_MASK) >> STAT_CECNT_SHIFT; in synps_edac_geterror_info()
163 p->ue_cnt = regval & STAT_UECNT_MASK; in synps_edac_geterror_info()
165 regval = readl(base + CE_LOG_OFST); in synps_edac_geterror_info()
166 if (!(p->ce_cnt && (regval & LOG_VALID))) in synps_edac_geterror_info()
169 p->ceinfo.bitpos = (regval & CE_LOG_BITPOS_MASK) >> CE_LOG_BITPOS_SHIFT; in synps_edac_geterror_info()
170 regval = readl(base + CE_ADDR_OFST); in synps_edac_geterror_info()
171 p->ceinfo.row = (regval & ADDR_ROW_MASK) >> ADDR_ROW_SHIFT; in synps_edac_geterror_info()
[all …]
/drivers/hwmon/
Dina2xx.c198 static int ina2xx_read_reg(struct device *dev, int reg, unsigned int *regval) in ina2xx_read_reg() argument
207 ret = regmap_read(data->regmap, reg, regval); in ina2xx_read_reg()
211 dev_dbg(dev, "read %d, val = 0x%04x\n", reg, *regval); in ina2xx_read_reg()
221 if (*regval == 0) { in ina2xx_read_reg()
257 unsigned int regval) in ina2xx_get_value() argument
264 val = DIV_ROUND_CLOSEST((s16)regval, data->config->shunt_div); in ina2xx_get_value()
267 val = (regval >> data->config->bus_voltage_shift) in ina2xx_get_value()
272 val = regval * data->power_lsb_uW; in ina2xx_get_value()
276 val = regval * data->current_lsb_uA; in ina2xx_get_value()
280 val = regval; in ina2xx_get_value()
[all …]
Dltc4245.c176 const u8 regval = data->vregs[reg - 0x10]; in ltc4245_get_voltage() local
182 voltage = regval * 55; in ltc4245_get_voltage()
186 voltage = regval * 22; in ltc4245_get_voltage()
190 voltage = regval * 15; in ltc4245_get_voltage()
194 voltage = regval * -55; in ltc4245_get_voltage()
197 voltage = regval * 10; in ltc4245_get_voltage()
212 const u8 regval = data->vregs[reg - 0x10]; in ltc4245_get_current() local
233 voltage = regval * 250; /* voltage in uV */ in ltc4245_get_current()
237 voltage = regval * 125; /* voltage in uV */ in ltc4245_get_current()
241 voltage = regval * 125; /* voltage in uV */ in ltc4245_get_current()
[all …]
Dtmp102.c85 unsigned int regval; in tmp102_read() local
107 err = regmap_read(tmp102->regmap, reg, &regval); in tmp102_read()
110 *temp = tmp102_reg_to_mC(regval); in tmp102_read()
224 unsigned int regval; in tmp102_probe() local
244 err = regmap_read(tmp102->regmap, TMP102_CONF_REG, &regval); in tmp102_probe()
250 if ((regval & ~TMP102_CONFREG_MASK) != in tmp102_probe()
256 tmp102->config_orig = regval; in tmp102_probe()
262 regval &= ~TMP102_CONFIG_CLEAR; in tmp102_probe()
263 regval |= TMP102_CONFIG_SET; in tmp102_probe()
265 err = regmap_write(tmp102->regmap, TMP102_CONF_REG, regval); in tmp102_probe()
Dk10temp.c78 u32 regval; in show_temp() local
84 &regval); in show_temp()
86 pci_read_config_dword(pdev, REG_REPORTED_TEMPERATURE, &regval); in show_temp()
88 return sprintf(buf, "%u\n", (regval >> 21) * 125); in show_temp()
102 u32 regval; in show_temp_crit() local
106 REG_HARDWARE_THERMAL_CONTROL, &regval); in show_temp_crit()
107 value = ((regval >> 16) & 0x7f) * 500 + 52000; in show_temp_crit()
109 value -= ((regval >> 24) & 0xf) * 500; in show_temp_crit()
/drivers/spi/
Dspi-rb4xx.c41 u32 regval; in do_spi_clk() local
43 regval = spi_ioc; in do_spi_clk()
45 regval |= AR71XX_SPI_IOC_DO; in do_spi_clk()
47 rb4xx_write(rbspi, AR71XX_SPI_REG_IOC, regval); in do_spi_clk()
48 rb4xx_write(rbspi, AR71XX_SPI_REG_IOC, regval | AR71XX_SPI_IOC_CLK); in do_spi_clk()
63 u32 regval; in do_spi_clk_two() local
65 regval = spi_ioc; in do_spi_clk_two()
67 regval |= AR71XX_SPI_IOC_DO; in do_spi_clk_two()
69 regval |= AR71XX_SPI_IOC_CS2; in do_spi_clk_two()
71 rb4xx_write(rbspi, AR71XX_SPI_REG_IOC, regval); in do_spi_clk_two()
[all …]
Dspi-sirf.c735 u32 regval; in spi_sirfsoc_chipselect() local
739 regval = readl(sspi->base + sspi->regs->spi_ctrl); in spi_sirfsoc_chipselect()
743 regval |= SIRFSOC_SPI_CS_IO_OUT; in spi_sirfsoc_chipselect()
745 regval &= ~SIRFSOC_SPI_CS_IO_OUT; in spi_sirfsoc_chipselect()
749 regval &= ~SIRFSOC_SPI_CS_IO_OUT; in spi_sirfsoc_chipselect()
751 regval |= SIRFSOC_SPI_CS_IO_OUT; in spi_sirfsoc_chipselect()
754 writel(regval, sspi->base + sspi->regs->spi_ctrl); in spi_sirfsoc_chipselect()
758 regval = readl(sspi->base + in spi_sirfsoc_chipselect()
763 regval |= SIRFSOC_USP_CS_HIGH_VALUE; in spi_sirfsoc_chipselect()
765 regval &= ~(SIRFSOC_USP_CS_HIGH_VALUE); in spi_sirfsoc_chipselect()
[all …]
/drivers/net/ethernet/synopsys/
Ddwc_eth_qos.c758 u32 regval; in dwceqos_mdio_read() local
762 regval = DWCEQOS_MDIO_PHYADDR(mii_id) | in dwceqos_mdio_read()
767 dwceqos_write(lp, REG_DWCEQOS_MAC_MDIO_ADDR, regval); in dwceqos_mdio_read()
789 u32 regval; in dwceqos_mdio_write() local
794 regval = DWCEQOS_MDIO_PHYADDR(mii_id) | in dwceqos_mdio_write()
799 dwceqos_write(lp, REG_DWCEQOS_MAC_MDIO_ADDR, regval); in dwceqos_mdio_write()
836 u32 regval; in dwceqos_link_down() local
841 regval = dwceqos_read(lp, REG_DWCEQOS_MAC_LPI_CTRL_STATUS); in dwceqos_link_down()
842 regval &= ~DWCEQOS_MAC_LPI_CTRL_STATUS_PLS; in dwceqos_link_down()
843 dwceqos_write(lp, REG_DWCEQOS_MAC_LPI_CTRL_STATUS, regval); in dwceqos_link_down()
[all …]
/drivers/iio/light/
Dmax44000.c206 u16 regval; in max44000_read_alsval() local
210 &regval, sizeof(regval)); in max44000_read_alsval()
217 regval = be16_to_cpu(regval); in max44000_read_alsval()
228 if (regval & MAX44000_ALSDATA_OVERFLOW) in max44000_read_alsval()
231 return regval << MAX44000_ALSTIM_SHIFT(alstim); in max44000_read_alsval()
247 unsigned int regval; in max44000_read_led_current_raw() local
250 ret = regmap_read(data->regmap, MAX44000_REG_CFG_TX, &regval); in max44000_read_led_current_raw()
253 regval &= MAX44000_LED_CURRENT_MASK; in max44000_read_led_current_raw()
254 if (regval >= 8) in max44000_read_led_current_raw()
255 regval -= 4; in max44000_read_led_current_raw()
[all …]
/drivers/net/ethernet/intel/i40e/
Di40e_ptp.c460 u32 tsyntype, regval; in i40e_ptp_set_timestamp_mode() local
525 regval = rd32(hw, I40E_PRTTSYN_CTL0); in i40e_ptp_set_timestamp_mode()
527 regval |= I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK; in i40e_ptp_set_timestamp_mode()
529 regval &= ~I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK; in i40e_ptp_set_timestamp_mode()
530 wr32(hw, I40E_PRTTSYN_CTL0, regval); in i40e_ptp_set_timestamp_mode()
532 regval = rd32(hw, I40E_PFINT_ICR0_ENA); in i40e_ptp_set_timestamp_mode()
534 regval |= I40E_PFINT_ICR0_ENA_TIMESYNC_MASK; in i40e_ptp_set_timestamp_mode()
536 regval &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK; in i40e_ptp_set_timestamp_mode()
537 wr32(hw, I40E_PFINT_ICR0_ENA, regval); in i40e_ptp_set_timestamp_mode()
545 regval = rd32(hw, I40E_PRTTSYN_CTL1); in i40e_ptp_set_timestamp_mode()
[all …]
/drivers/i2c/busses/
Di2c-sirf.c105 u32 regval; in i2c_sirfsoc_queue_cmd() local
111 regval = SIRFSOC_I2C_READ | SIRFSOC_I2C_CMD_RP(0); in i2c_sirfsoc_queue_cmd()
114 regval |= SIRFSOC_I2C_STOP | SIRFSOC_I2C_NACK; in i2c_sirfsoc_queue_cmd()
115 writel(regval, in i2c_sirfsoc_queue_cmd()
124 regval = SIRFSOC_I2C_WRITE | SIRFSOC_I2C_CMD_RP(0); in i2c_sirfsoc_queue_cmd()
127 regval |= SIRFSOC_I2C_STOP; in i2c_sirfsoc_queue_cmd()
128 writel(regval, in i2c_sirfsoc_queue_cmd()
185 u32 regval = SIRFSOC_I2C_START | SIRFSOC_I2C_CMD_RP(0) | SIRFSOC_I2C_WRITE; in i2c_sirfsoc_set_address() local
189 regval |= SIRFSOC_I2C_STOP; in i2c_sirfsoc_set_address()
191 writel(regval, siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++)); in i2c_sirfsoc_set_address()
[all …]
/drivers/video/fbdev/core/
Dsvgalib.c25 u8 regval, bitval, bitnum; in svga_wcrt_multi() local
28 regval = vga_rcrt(regbase, regset->regnum); in svga_wcrt_multi()
32 regval = regval & ~bitval; in svga_wcrt_multi()
33 if (value & 1) regval = regval | bitval; in svga_wcrt_multi()
37 vga_wcrt(regbase, regset->regnum, regval); in svga_wcrt_multi()
45 u8 regval, bitval, bitnum; in svga_wseq_multi() local
48 regval = vga_rseq(regbase, regset->regnum); in svga_wseq_multi()
52 regval = regval & ~bitval; in svga_wseq_multi()
53 if (value & 1) regval = regval | bitval; in svga_wseq_multi()
57 vga_wseq(regbase, regset->regnum, regval); in svga_wseq_multi()
[all …]
/drivers/iio/adc/
Dtwl4030-madc.c683 u8 regval; in twl4030_madc_set_current_generator() local
686 &regval, TWL4030_BCI_BCICTL1); in twl4030_madc_set_current_generator()
695 regval |= regmask; in twl4030_madc_set_current_generator()
697 regval &= ~regmask; in twl4030_madc_set_current_generator()
700 regval, TWL4030_BCI_BCICTL1); in twl4030_madc_set_current_generator()
718 u8 regval; in twl4030_madc_set_power() local
722 &regval, TWL4030_MADC_CTRL1); in twl4030_madc_set_power()
729 regval |= TWL4030_MADC_MADCON; in twl4030_madc_set_power()
731 regval &= ~TWL4030_MADC_MADCON; in twl4030_madc_set_power()
732 ret = twl_i2c_write_u8(TWL4030_MODULE_MADC, regval, TWL4030_MADC_CTRL1); in twl4030_madc_set_power()
[all …]
/drivers/staging/iio/cdc/
Dad7152.c98 u8 regval) in ad7152_start_calib() argument
114 regval |= AD7152_CONF_CH1EN; in ad7152_start_calib()
116 regval |= AD7152_CONF_CH2EN; in ad7152_start_calib()
119 ret = i2c_smbus_write_byte_data(chip->client, AD7152_REG_CFG, regval); in ad7152_start_calib()
132 } while ((ret == regval) && timeout--); in ad7152_start_calib()
327 u8 regval = 0; in ad7152_read_raw() local
335 regval = chip->setup[chan->channel]; in ad7152_read_raw()
342 if (regval != chip->setup[chan->channel]) { in ad7152_read_raw()
351 regval = AD7152_CONF_CH1EN; in ad7152_read_raw()
353 regval = AD7152_CONF_CH2EN; in ad7152_read_raw()
[all …]

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