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Searched refs:smumgr (Results 1 – 25 of 26) sorted by relevance

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/drivers/gpu/drm/amd/powerplay/smumgr/
Dsmumgr.c35 struct pp_smumgr *smumgr; in smum_init() local
40 smumgr = kzalloc(sizeof(struct pp_smumgr), GFP_KERNEL); in smum_init()
41 if (smumgr == NULL) in smum_init()
44 smumgr->device = pp_init->device; in smum_init()
45 smumgr->chip_family = pp_init->chip_family; in smum_init()
46 smumgr->chip_id = pp_init->chip_id; in smum_init()
47 smumgr->usec_timeout = AMD_MAX_USEC_TIMEOUT; in smum_init()
48 smumgr->reload_fw = 1; in smum_init()
49 handle->smu_mgr = smumgr; in smum_init()
51 switch (smumgr->chip_family) { in smum_init()
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Dcz_smumgr.c53 static int cz_smum_get_argument(struct pp_smumgr *smumgr) in cz_smum_get_argument() argument
55 if (smumgr == NULL || smumgr->device == NULL) in cz_smum_get_argument()
58 return cgs_read_register(smumgr->device, in cz_smum_get_argument()
62 static int cz_send_msg_to_smc_async(struct pp_smumgr *smumgr, in cz_send_msg_to_smc_async() argument
67 if (smumgr == NULL || smumgr->device == NULL) in cz_send_msg_to_smc_async()
70 result = SMUM_WAIT_FIELD_UNEQUAL(smumgr, in cz_send_msg_to_smc_async()
77 cgs_write_register(smumgr->device, mmSMU_MP1_SRBM2P_RESP_0, 0); in cz_send_msg_to_smc_async()
78 cgs_write_register(smumgr->device, mmSMU_MP1_SRBM2P_MSG_0, msg); in cz_send_msg_to_smc_async()
84 static int cz_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg) in cz_send_msg_to_smc() argument
88 result = cz_send_msg_to_smc_async(smumgr, msg); in cz_send_msg_to_smc()
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Dfiji_smumgr.c61 static int fiji_start_smu_in_protection_mode(struct pp_smumgr *smumgr) in fiji_start_smu_in_protection_mode() argument
69 SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, in fiji_start_smu_in_protection_mode()
72 result = smu7_upload_smu_firmware_image(smumgr); in fiji_start_smu_in_protection_mode()
77 cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC, in fiji_start_smu_in_protection_mode()
80 SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, in fiji_start_smu_in_protection_mode()
84 SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, in fiji_start_smu_in_protection_mode()
92 SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, in fiji_start_smu_in_protection_mode()
96 cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC, in fiji_start_smu_in_protection_mode()
99 SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, RCU_UC_EVENTS, in fiji_start_smu_in_protection_mode()
102 cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, 0x20000); in fiji_start_smu_in_protection_mode()
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Dsmu7_smumgr.c37 static int smu7_set_smc_sram_address(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t limit) in smu7_set_smc_sram_address() argument
42 cgs_write_register(smumgr->device, mmSMC_IND_INDEX_11, smc_addr); in smu7_set_smc_sram_address()
43 …SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 0); /* on ci, SMC_IND… in smu7_set_smc_sram_address()
48 int smu7_copy_bytes_from_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address, uint32_t *dest, … in smu7_copy_bytes_from_smc() argument
62 smu7_read_smc_sram_dword(smumgr, addr, &data, limit); in smu7_copy_bytes_from_smc()
72 smu7_read_smc_sram_dword(smumgr, addr, &data, limit); in smu7_copy_bytes_from_smc()
84 int smu7_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address, in smu7_copy_bytes_to_smc() argument
102 result = smu7_set_smc_sram_address(smumgr, addr, limit); in smu7_copy_bytes_to_smc()
107 cgs_write_register(smumgr->device, mmSMC_IND_DATA_11, data); in smu7_copy_bytes_to_smc()
118 result = smu7_set_smc_sram_address(smumgr, addr, limit); in smu7_copy_bytes_to_smc()
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Dpolaris10_smumgr.c64 static int polaris10_setup_pwr_virus(struct pp_smumgr *smumgr) in polaris10_setup_pwr_virus() argument
71 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend); in polaris10_setup_pwr_virus()
79 cgs_write_register(smumgr->device, reg, data); in polaris10_setup_pwr_virus()
98 static int polaris10_perform_btc(struct pp_smumgr *smumgr) in polaris10_perform_btc() argument
101 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend); in polaris10_perform_btc()
104 …if (0 != smu7_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_PerformBtc, smu_data->avfs.avfs_btc… in polaris10_perform_btc()
112 cgs_write_register(smumgr->device, mmCP_MEC_CNTL, 0x50000000); in polaris10_perform_btc()
114 cgs_write_register(smumgr->device, mmGRBM_SOFT_RESET, 0xffffffff); in polaris10_perform_btc()
115 cgs_write_register(smumgr->device, mmGRBM_SOFT_RESET, 0); in polaris10_perform_btc()
121 int polaris10_setup_graphics_level_structure(struct pp_smumgr *smumgr) in polaris10_setup_graphics_level_structure() argument
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Diceland_smumgr.c42 static int iceland_start_smc(struct pp_smumgr *smumgr) in iceland_start_smc() argument
44 SMUM_WRITE_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, in iceland_start_smc()
50 static void iceland_reset_smc(struct pp_smumgr *smumgr) in iceland_reset_smc() argument
52 SMUM_WRITE_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, in iceland_reset_smc()
58 static void iceland_stop_smc_clock(struct pp_smumgr *smumgr) in iceland_stop_smc_clock() argument
60 SMUM_WRITE_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, in iceland_stop_smc_clock()
65 static void iceland_start_smc_clock(struct pp_smumgr *smumgr) in iceland_start_smc_clock() argument
67 SMUM_WRITE_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, in iceland_start_smc_clock()
72 static int iceland_smu_start_smc(struct pp_smumgr *smumgr) in iceland_smu_start_smc() argument
75 smu7_program_jump_on_start(smumgr); in iceland_smu_start_smc()
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Dtonga_smumgr.c40 static int tonga_start_in_protection_mode(struct pp_smumgr *smumgr) in tonga_start_in_protection_mode() argument
45 SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, in tonga_start_in_protection_mode()
48 result = smu7_upload_smu_firmware_image(smumgr); in tonga_start_in_protection_mode()
53 cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC, in tonga_start_in_protection_mode()
57 SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, in tonga_start_in_protection_mode()
61 SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, in tonga_start_in_protection_mode()
65 SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, in tonga_start_in_protection_mode()
69 cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC, in tonga_start_in_protection_mode()
72 SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, in tonga_start_in_protection_mode()
78 smu7_send_msg_to_smc_offset(smumgr); in tonga_start_in_protection_mode()
[all …]
Dsmu7_smumgr.h59 int smu7_copy_bytes_from_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address,
61 int smu7_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address,
63 int smu7_program_jump_on_start(struct pp_smumgr *smumgr);
64 bool smu7_is_smc_ram_running(struct pp_smumgr *smumgr);
65 int smu7_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg);
66 int smu7_send_msg_to_smc_without_waiting(struct pp_smumgr *smumgr, uint16_t msg);
67 int smu7_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr, uint16_t msg,
69 int smu7_send_msg_to_smc_with_parameter_without_waiting(struct pp_smumgr *smumgr,
71 int smu7_send_msg_to_smc_offset(struct pp_smumgr *smumgr);
72 int smu7_wait_for_smc_inactive(struct pp_smumgr *smumgr);
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Dpolaris10_smc.c151 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); in polaris10_populate_bapm_parameters_in_dpm_table()
199 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); in polaris10_populate_svi_load_line()
213 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); in polaris10_populate_tdc_limit()
230 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); in polaris10_populate_dw8()
234 if (smu7_read_smc_sram_dword(hwmgr->smumgr, in polaris10_populate_dw8()
255 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); in polaris10_populate_temperature_scaler()
266 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); in polaris10_populate_fuzzy_fan()
282 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); in polaris10_populate_gnb_lpml()
298 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); in polaris10_populate_bapm_vddc_base_leakage_sidd()
318 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); in polaris10_populate_pm_fuses()
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Diceland_smc.c104 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); in iceland_initialize_power_tune_defaults()
133 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); in iceland_populate_svi_load_line()
147 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); in iceland_populate_tdc_limit()
162 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); in iceland_populate_dw8()
166 if (smu7_read_smc_sram_dword(hwmgr->smumgr, in iceland_populate_dw8()
187 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); in iceland_populate_gnb_lpml()
203 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); in iceland_populate_bapm_vddc_base_leakage_sidd()
222 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); in iceland_populate_bapm_vddc_vid_sidd()
248 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); in iceland_populate_vddc_vid()
267 struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smumgr->backend); in iceland_populate_pm_fuses()
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Dfiji_smc.c201 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); in fiji_initialize_power_tune_defaults()
219 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); in fiji_populate_bapm_parameters_in_dpm_table()
302 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); in fiji_populate_svi_load_line()
317 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); in fiji_populate_tdc_limit()
337 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); in fiji_populate_dw8()
341 if (smu7_read_smc_sram_dword(hwmgr->smumgr, in fiji_populate_dw8()
362 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); in fiji_populate_temperature_scaler()
373 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); in fiji_populate_fuzzy_fan()
392 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); in fiji_populate_gnb_lpml()
408 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend); in fiji_populate_bapm_vddc_base_leakage_sidd()
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Dtonga_smc.c409 struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smumgr->backend); in tonga_populate_smc_link_level()
601 struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smumgr->backend); in tonga_populate_all_graphic_levels()
693 result = smu7_copy_bytes_to_smc(hwmgr->smumgr, level_array_address, in tonga_populate_all_graphic_levels()
1005 (struct tonga_smumgr *)(hwmgr->smumgr->backend); in tonga_populate_all_memory_levels()
1051 result = smu7_copy_bytes_to_smc(hwmgr->smumgr, in tonga_populate_all_memory_levels()
1093 (struct tonga_smumgr *)(hwmgr->smumgr->backend); in tonga_populate_smc_acpi_level()
1457 (struct tonga_smumgr *)(hwmgr->smumgr->backend); in tonga_program_memory_timing_parameters()
1478 hwmgr->smumgr, in tonga_program_memory_timing_parameters()
1495 (struct tonga_smumgr *)(hwmgr->smumgr->backend); in tonga_populate_smc_boot_level()
1546 (struct tonga_smumgr *)(hwmgr->smumgr->backend); in tonga_populate_clock_stretcher_data_table()
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DMakefile5 SMU_MGR = smumgr.o cz_smumgr.o tonga_smumgr.o fiji_smumgr.o fiji_smc.o \
9 AMD_PP_SMUMGR = $(addprefix $(AMD_PP_PATH)/smumgr/,$(SMU_MGR))
Dcz_smumgr.h100 extern int cz_smum_init(struct pp_smumgr *smumgr);
/drivers/gpu/drm/amd/powerplay/inc/
Dsmumgr.h97 int (*smu_init)(struct pp_smumgr *smumgr);
98 int (*smu_fini)(struct pp_smumgr *smumgr);
99 int (*start_smu)(struct pp_smumgr *smumgr);
100 int (*check_fw_load_finish)(struct pp_smumgr *smumgr,
102 int (*request_smu_load_fw)(struct pp_smumgr *smumgr);
103 int (*request_smu_load_specific_fw)(struct pp_smumgr *smumgr,
105 int (*get_argument)(struct pp_smumgr *smumgr);
106 int (*send_msg_to_smc)(struct pp_smumgr *smumgr, uint16_t msg);
107 int (*send_msg_to_smc_with_parameter)(struct pp_smumgr *smumgr,
109 int (*download_pptable_settings)(struct pp_smumgr *smumgr,
[all …]
Deventmgr.h103 struct pp_smumgr *smumgr; member
/drivers/gpu/drm/amd/powerplay/hwmgr/
Dsmu7_clockpowergating.c30 return smum_send_msg_to_smc(hwmgr->smumgr, enable ? in smu7_enable_disable_uvd_dpm()
37 return smum_send_msg_to_smc(hwmgr->smumgr, enable ? in smu7_enable_disable_vce_dpm()
44 return smum_send_msg_to_smc(hwmgr->smumgr, enable ? in smu7_enable_disable_samu_dpm()
73 return smum_send_msg_to_smc(hwmgr->smumgr, in smu7_powerdown_uvd()
83 return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, in smu7_powerup_uvd()
86 return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, in smu7_powerup_uvd()
97 return smum_send_msg_to_smc(hwmgr->smumgr, in smu7_powerdown_vce()
105 return smum_send_msg_to_smc(hwmgr->smumgr, in smu7_powerup_vce()
114 return smum_send_msg_to_smc(hwmgr->smumgr, in smu7_powerdown_samu()
123 return smum_send_msg_to_smc(hwmgr->smumgr, in smu7_powerup_samu()
[all …]
Dcz_hwmgr.c166 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetMaxSclkLevel); in cz_get_max_sclk_level()
167 cz_hwmgr->max_sclk_level = smum_get_argument(hwmgr->smumgr) + 1; in cz_get_max_sclk_level()
473 ret = smum_download_powerplay_table(hwmgr->smumgr, &table); in cz_tf_upload_pptable_to_smu()
565 ret = smum_upload_powerplay_table(hwmgr->smumgr); in cz_tf_upload_pptable_to_smu()
611 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetMaxUvdLevel); in cz_tf_init_uvd_limit()
612 level = smum_get_argument(hwmgr->smumgr); in cz_tf_init_uvd_limit()
639 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetMaxEclkLevel); in cz_tf_init_vce_limit()
640 level = smum_get_argument(hwmgr->smumgr); in cz_tf_init_vce_limit()
667 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetMaxAclkLevel); in cz_tf_init_acp_limit()
668 level = smum_get_argument(hwmgr->smumgr); in cz_tf_init_acp_limit()
[all …]
Dsmu7_hwmgr.c161 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Voltage_Cntl_Enable); in smu7_enable_smc_voltage_controller()
298 tmp = smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_VDDC); in smu7_construct_voltage_tables()
305 tmp = smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_VDDGFX); in smu7_construct_voltage_tables()
312 tmp = smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_VDDCI); in smu7_construct_voltage_tables()
319 tmp = smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_MVDD); in smu7_construct_voltage_tables()
491 return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_ResetToDefaults); in smu7_reset_to_default()
549 tmp = smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_LINK); in smu7_setup_default_pcie_table()
623 smum_get_mac_definition(hwmgr->smumgr, in smu7_reset_dpm_tables()
628 smum_get_mac_definition(hwmgr->smumgr, in smu7_reset_dpm_tables()
633 smum_get_mac_definition(hwmgr->smumgr, in smu7_reset_dpm_tables()
[all …]
Dcz_clockpowergating.c126 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, in cz_enable_disable_uvd_dpm()
131 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, in cz_enable_disable_uvd_dpm()
147 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, in cz_enable_disable_vce_dpm()
152 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, in cz_enable_disable_vce_dpm()
Dsmu7_thermal.c159 result = smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_StartFanControl); in smu7_fan_ctrl_start_smc_fan_control()
173 result = smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_StartFanControl); in smu7_fan_ctrl_start_smc_fan_control()
178 result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, in smu7_fan_ctrl_start_smc_fan_control()
189 return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_StopFanControl); in smu7_fan_ctrl_stop_smc_fan_control()
380 return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Thermal_Cntl_Enable); in smu7_thermal_enable_alert()
398 return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Thermal_Cntl_Disable); in smu7_thermal_disable_alert()
Dsmu7_powertune.c424 …result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_Didt_Block_Function, DIDTBlo… in smu7_enable_didt()
568 smc_result = smum_send_msg_to_smc(hwmgr->smumgr, in smu7_enable_smc_cac()
585 int smc_result = smum_send_msg_to_smc(hwmgr->smumgr, in smu7_disable_smc_cac()
601 return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, in smu7_set_power_limit()
608 return smum_send_msg_to_smc_with_parameter(pHwMgr->smumgr, in smu7_set_overdriver_target_tdp()
631 smc_result = smum_send_msg_to_smc(hwmgr->smumgr, in smu7_enable_power_containment()
641 smc_result = smum_send_msg_to_smc(hwmgr->smumgr, in smu7_enable_power_containment()
672 smc_result = smum_send_msg_to_smc(hwmgr->smumgr, in smu7_disable_power_containment()
681 smc_result = smum_send_msg_to_smc(hwmgr->smumgr, in smu7_disable_power_containment()
690 smc_result = smum_send_msg_to_smc(hwmgr->smumgr, in smu7_disable_power_containment()
Dhwmgr.c64 hwmgr->smumgr = handle->smu_mgr; in hwmgr_init()
625 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, in phm_apply_dal_min_voltage_request()
/drivers/gpu/drm/amd/powerplay/
Damd_powerplay.c116 struct pp_smumgr *smumgr; in pp_hw_init() local
124 smumgr = pp_handle->smu_mgr; in pp_hw_init()
126 if (smumgr == NULL || smumgr->smumgr_funcs == NULL || in pp_hw_init()
127 smumgr->smumgr_funcs->smu_init == NULL || in pp_hw_init()
128 smumgr->smumgr_funcs->start_smu == NULL) in pp_hw_init()
131 ret = smumgr->smumgr_funcs->smu_init(smumgr); in pp_hw_init()
137 ret = smumgr->smumgr_funcs->start_smu(smumgr); in pp_hw_init()
140 smumgr->smumgr_funcs->smu_fini(smumgr); in pp_hw_init()
157 struct pp_smumgr *smumgr; in pp_hw_fini() local
169 smumgr = pp_handle->smu_mgr; in pp_hw_fini()
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DMakefile6 -I$(FULL_AMD_PATH)/powerplay/smumgr\
12 PP_LIBS = smumgr hwmgr eventmgr

12