| /drivers/media/pci/cx25821/ |
| D | cx25821-medusa-video.c | 38 u32 value = 0; in medusa_enable_bluefield_output() local
77 value = cx25821_i2c_read(&dev->i2c_bus[0], out_ctrl, &tmp); in medusa_enable_bluefield_output()
78 value &= 0xFFFFFF7F; /* clear BLUE_FIELD_EN */ in medusa_enable_bluefield_output()
80 value |= 0x00000080; /* set BLUE_FIELD_EN */ in medusa_enable_bluefield_output()
81 cx25821_i2c_write(&dev->i2c_bus[0], out_ctrl, value); in medusa_enable_bluefield_output()
83 value = cx25821_i2c_read(&dev->i2c_bus[0], out_ctrl_ns, &tmp); in medusa_enable_bluefield_output()
84 value &= 0xFFFFFF7F; in medusa_enable_bluefield_output()
86 value |= 0x00000080; /* set BLUE_FIELD_EN */ in medusa_enable_bluefield_output()
87 cx25821_i2c_write(&dev->i2c_bus[0], out_ctrl_ns, value); in medusa_enable_bluefield_output()
94 u32 value = 0; in medusa_initialize_ntsc() local
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| /drivers/video/fbdev/riva/ |
| D | nvreg.h | 34 #define SetBF(mask,value) ((value) << (0?mask)) argument
37 #define MaskAndSetBF(var,mask,value) (var)=(((var)&(~MASKEXPAND(mask)) \ argument
38 | SetBF(mask,value)))
47 #define DEVICE_WRITE(device,reg,value) DEVICE_ACCESS(device,reg)=(value) argument
51 #define DEVICE_DEF(device,mask,value) \ argument
52 SetBF(NV_##device##_##mask,NV_##device##_##mask##_##value)
53 #define DEVICE_VALUE(device,mask,value) SetBF(NV_##device##_##mask,value) argument
56 #define PDAC_Write(reg,value) DEVICE_WRITE(PDAC,reg,value) argument
59 #define PDAC_Def(mask,value) DEVICE_DEF(PDAC,mask,value) argument
60 #define PDAC_Val(mask,value) DEVICE_VALUE(PDAC,mask,value) argument
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| /drivers/gpu/drm/tegra/ |
| D | sor.c | 240 static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value, in tegra_sor_writel() argument
243 writel(value, sor->regs + (offset << 2)); in tegra_sor_writel()
281 u32 value; in tegra_clk_sor_brick_set_parent() local
283 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_clk_sor_brick_set_parent()
284 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; in tegra_clk_sor_brick_set_parent()
288 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK; in tegra_clk_sor_brick_set_parent()
292 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK; in tegra_clk_sor_brick_set_parent()
296 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_clk_sor_brick_set_parent()
306 u32 value; in tegra_clk_sor_brick_get_parent() local
308 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_clk_sor_brick_get_parent()
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| /drivers/phy/tegra/ |
| D | xusb-tegra210.c | 255 u32 value; in tegra210_pex_uphy_enable() local
271 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
272 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_MASK << in tegra210_pex_uphy_enable()
274 value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_VAL << in tegra210_pex_uphy_enable()
276 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
278 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL5); in tegra210_pex_uphy_enable()
279 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_MASK << in tegra210_pex_uphy_enable()
281 value |= XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_VAL << in tegra210_pex_uphy_enable()
283 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL5); in tegra210_pex_uphy_enable()
285 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
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| D | xusb-tegra124.c | 235 u32 value; in tegra124_xusb_padctl_enable() local
242 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); in tegra124_xusb_padctl_enable()
243 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN; in tegra124_xusb_padctl_enable()
244 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); in tegra124_xusb_padctl_enable()
248 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); in tegra124_xusb_padctl_enable()
249 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY; in tegra124_xusb_padctl_enable()
250 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); in tegra124_xusb_padctl_enable()
254 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); in tegra124_xusb_padctl_enable()
255 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN; in tegra124_xusb_padctl_enable()
256 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); in tegra124_xusb_padctl_enable()
[all …]
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| /drivers/net/ethernet/sfc/ |
| D | io.h | 82 static inline void _efx_writeq(struct efx_nic *efx, __le64 value, in _efx_writeq() argument
85 __raw_writeq((__force u64)value, efx->membase + reg); in _efx_writeq()
93 static inline void _efx_writed(struct efx_nic *efx, __le32 value, in _efx_writed() argument
96 __raw_writel((__force u32)value, efx->membase + reg); in _efx_writed()
104 static inline void efx_writeo(struct efx_nic *efx, const efx_oword_t *value, in efx_writeo() argument
111 EFX_OWORD_VAL(*value)); in efx_writeo()
115 _efx_writeq(efx, value->u64[0], reg + 0); in efx_writeo()
116 _efx_writeq(efx, value->u64[1], reg + 8); in efx_writeo()
118 _efx_writed(efx, value->u32[0], reg + 0); in efx_writeo()
119 _efx_writed(efx, value->u32[1], reg + 4); in efx_writeo()
[all …]
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| /drivers/media/usb/cx231xx/ |
| D | cx231xx-avcore.c | 77 u32 value = 0; in initGPIO() local
82 cx231xx_send_gpio_cmd(dev, _gpio_direction, (u8 *)&value, 4, 0, 0); in initGPIO()
98 u8 value[4] = { 0, 0, 0, 0 }; in uninitGPIO() local
103 0x68, value, 4); in uninitGPIO()
274 u8 value = 0; in cx231xx_afe_set_input_mux() local
277 status = afe_read_byte(dev, ADC_INPUT_CH1, &value); in cx231xx_afe_set_input_mux()
278 value &= ~INPUT_SEL_MASK; in cx231xx_afe_set_input_mux()
279 value |= (ch1_setting - 1) << 4; in cx231xx_afe_set_input_mux()
280 value &= 0xff; in cx231xx_afe_set_input_mux()
281 status = afe_write_byte(dev, ADC_INPUT_CH1, value); in cx231xx_afe_set_input_mux()
[all …]
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| /drivers/gpu/drm/radeon/ |
| D | radeon_kms.c | 185 uint32_t *value) in radeon_set_filp_rights() argument
190 if (*value == 1) { in radeon_set_filp_rights()
194 } else if (*value == 0) { in radeon_set_filp_rights()
199 *value = *owner == applier ? 1 : 0; in radeon_set_filp_rights()
223 uint32_t *value, value_tmp, *value_ptr, value_size; in radeon_info_ioctl() local
228 value_ptr = (uint32_t *)((unsigned long)info->value); in radeon_info_ioctl()
229 value = &value_tmp; in radeon_info_ioctl()
234 *value = dev->pdev->device; in radeon_info_ioctl()
237 *value = rdev->num_gb_pipes; in radeon_info_ioctl()
240 *value = rdev->num_z_pipes; in radeon_info_ioctl()
[all …]
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| /drivers/target/iscsi/ |
| D | iscsi_target_parameters.c | 123 pr_debug("%s: %s\n", param->name, param->value); in iscsi_print_params()
127 char *name, char *value, u8 phase, u8 scope, u8 sender, in iscsi_set_default_param() argument
145 param->value = kstrdup(value, GFP_KERNEL); in iscsi_set_default_param()
146 if (!param->value) { in iscsi_set_default_param()
193 kfree(param->value); in iscsi_set_default_param()
466 if (param->value) in iscsi_set_keys_to_negotiate()
601 new_param->value = kstrdup(param->value, GFP_KERNEL); in iscsi_copy_param_list()
602 if (!new_param->value || !new_param->name) { in iscsi_copy_param_list()
603 kfree(new_param->value); in iscsi_copy_param_list()
655 kfree(param->value); in iscsi_release_param_list()
[all …]
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| /drivers/iio/common/hid-sensors/ |
| D | hid-sensor-attributes.c | 109 static void convert_from_vtf_format(u32 value, int size, int exp, in convert_from_vtf_format() argument
114 if (value & BIT(size*8 - 1)) { in convert_from_vtf_format()
115 value = ((1LL << (size * 8)) - value); in convert_from_vtf_format()
120 *val1 = sign * value * pow_10(exp); in convert_from_vtf_format()
123 split_micro_fraction(value, -exp, val1, val2); in convert_from_vtf_format()
133 u32 value; in convert_to_vtf_format() local
140 value = abs(val1) * pow_10(-exp); in convert_to_vtf_format()
141 value += abs(val2) / pow_10(6+exp); in convert_to_vtf_format()
143 value = abs(val1) / pow_10(exp); in convert_to_vtf_format()
145 value = ((1LL << (size * 8)) - value); in convert_to_vtf_format()
[all …]
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| /drivers/video/fbdev/core/ |
| D | svgalib.c | 23 void svga_wcrt_multi(void __iomem *regbase, const struct vga_regset *regset, u32 value) in svga_wcrt_multi() argument
33 if (value & 1) regval = regval | bitval; in svga_wcrt_multi()
35 value = value >> 1; in svga_wcrt_multi()
43 void svga_wseq_multi(void __iomem *regbase, const struct vga_regset *regset, u32 value) in svga_wseq_multi() argument
53 if (value & 1) regval = regval | bitval; in svga_wseq_multi()
55 value = value >> 1; in svga_wseq_multi()
445 u32 value; in svga_check_timings() local
453 value = var->xres + var->left_margin + var->right_margin + var->hsync_len; in svga_check_timings()
454 if (((value / 8) - 5) >= svga_regset_size (tm->h_total_regs)) in svga_check_timings()
458 value = var->xres; in svga_check_timings()
[all …]
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| /drivers/pinctrl/tegra/ |
| D | pinctrl-tegra-xusb.c | 101 static inline void padctl_writel(struct tegra_xusb_padctl *padctl, u32 value, in padctl_writel() argument
104 writel(value, padctl->regs + offset); in padctl_writel()
154 #define TEGRA_XUSB_PADCTL_PACK(param, value) ((param) << 16 | (value)) argument
169 u32 value; in tegra_xusb_padctl_parse_subnode() local
180 err = of_property_read_u32(np, properties[i].name, &value); in tegra_xusb_padctl_parse_subnode()
188 config = TEGRA_XUSB_PADCTL_PACK(properties[i].param, value); in tegra_xusb_padctl_parse_subnode()
309 u32 value; in tegra_xusb_padctl_pinmux_set() local
320 value = padctl_readl(padctl, lane->offset); in tegra_xusb_padctl_pinmux_set()
321 value &= ~(lane->mask << lane->shift); in tegra_xusb_padctl_pinmux_set()
322 value |= i << lane->shift; in tegra_xusb_padctl_pinmux_set()
[all …]
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| /drivers/net/ethernet/stmicro/stmmac/ |
| D | dwmac1000_core.c | 39 u32 value = readl(ioaddr + GMAC_CONTROL); in dwmac1000_core_init() local
42 value |= GMAC_CORE_INIT; in dwmac1000_core_init()
45 value |= GMAC_CONTROL_2K; in dwmac1000_core_init()
47 value |= GMAC_CONTROL_JE; in dwmac1000_core_init()
50 value |= GMAC_CONTROL_TE; in dwmac1000_core_init()
53 value &= ~GMAC_CONTROL_PS; in dwmac1000_core_init()
55 value |= GMAC_CONTROL_PS; in dwmac1000_core_init()
58 value &= ~GMAC_CONTROL_FES; in dwmac1000_core_init()
60 value |= GMAC_CONTROL_FES; in dwmac1000_core_init()
64 writel(value, ioaddr + GMAC_CONTROL); in dwmac1000_core_init()
[all …]
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| D | dwmac4_lib.c | 19 u32 value = readl(ioaddr + DMA_BUS_MODE); in dwmac4_dma_reset() local
23 value |= DMA_BUS_MODE_SFT_RESET; in dwmac4_dma_reset()
24 writel(value, ioaddr + DMA_BUS_MODE); in dwmac4_dma_reset()
50 u32 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(STMMAC_CHAN0)); in dwmac4_dma_start_tx() local
52 value |= DMA_CONTROL_ST; in dwmac4_dma_start_tx()
53 writel(value, ioaddr + DMA_CHAN_TX_CONTROL(STMMAC_CHAN0)); in dwmac4_dma_start_tx()
55 value = readl(ioaddr + GMAC_CONFIG); in dwmac4_dma_start_tx()
56 value |= GMAC_CONFIG_TE; in dwmac4_dma_start_tx()
57 writel(value, ioaddr + GMAC_CONFIG); in dwmac4_dma_start_tx()
62 u32 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(STMMAC_CHAN0)); in dwmac4_dma_stop_tx() local
[all …]
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| D | dwmac4_core.c | 26 u32 value = readl(ioaddr + GMAC_CONFIG); in dwmac4_core_init() local
28 value |= GMAC_CORE_INIT; in dwmac4_core_init()
31 value |= GMAC_CONFIG_2K; in dwmac4_core_init()
33 value |= GMAC_CONFIG_JE; in dwmac4_core_init()
36 value |= GMAC_CONFIG_TE; in dwmac4_core_init()
39 value &= ~GMAC_CONFIG_PS; in dwmac4_core_init()
41 value |= GMAC_CONFIG_PS; in dwmac4_core_init()
44 value &= ~GMAC_CONFIG_FES; in dwmac4_core_init()
46 value |= GMAC_CONFIG_FES; in dwmac4_core_init()
50 writel(value, ioaddr + GMAC_CONFIG); in dwmac4_core_init()
[all …]
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| D | dwmac4_dma.c | 22 u32 value = readl(ioaddr + DMA_SYS_BUS_MODE); in dwmac4_dma_axi() local
26 (value & DMA_SYS_BUS_FB) ? "fixed" : "any"); in dwmac4_dma_axi()
29 value |= DMA_AXI_EN_LPI; in dwmac4_dma_axi()
31 value |= DMA_AXI_LPI_XIT_FRM; in dwmac4_dma_axi()
33 value &= ~DMA_AXI_WR_OSR_LMT; in dwmac4_dma_axi()
34 value |= (axi->axi_wr_osr_lmt & DMA_AXI_OSR_MAX) << in dwmac4_dma_axi()
37 value &= ~DMA_AXI_RD_OSR_LMT; in dwmac4_dma_axi()
38 value |= (axi->axi_rd_osr_lmt & DMA_AXI_OSR_MAX) << in dwmac4_dma_axi()
48 value |= DMA_AXI_BLEN256; in dwmac4_dma_axi()
51 value |= DMA_AXI_BLEN128; in dwmac4_dma_axi()
[all …]
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| /drivers/gpu/drm/i915/ |
| D | dvo_ns2501.c | 195 uint8_t value; member
300 [0] = { .offset = 0x0a, .value = 0x81, },
302 [1] = { .offset = 0x12, .value = 0x02, },
303 [2] = { .offset = 0x18, .value = 0x07, },
304 [3] = { .offset = 0x19, .value = 0x00, },
305 [4] = { .offset = 0x1a, .value = 0x00, }, /* PLL?, ignored */
307 [5] = { .offset = 0x1e, .value = 0x02, },
308 [6] = { .offset = 0x1f, .value = 0x40, },
309 [7] = { .offset = 0x20, .value = 0x00, },
310 [8] = { .offset = 0x21, .value = 0x00, },
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| /drivers/usb/gadget/udc/ |
| D | fotg210-udc.c | 33 u32 value = ioread32(ep->fotg210->reg + FOTG210_DMISGR1); in fotg210_disable_fifo_int() local
36 value |= DMISGR1_MF_IN_INT(ep->epnum - 1); in fotg210_disable_fifo_int()
38 value |= DMISGR1_MF_OUTSPK_INT(ep->epnum - 1); in fotg210_disable_fifo_int()
39 iowrite32(value, ep->fotg210->reg + FOTG210_DMISGR1); in fotg210_disable_fifo_int()
44 u32 value = ioread32(ep->fotg210->reg + FOTG210_DMISGR1); in fotg210_enable_fifo_int() local
47 value &= ~DMISGR1_MF_IN_INT(ep->epnum - 1); in fotg210_enable_fifo_int()
49 value &= ~DMISGR1_MF_OUTSPK_INT(ep->epnum - 1); in fotg210_enable_fifo_int()
50 iowrite32(value, ep->fotg210->reg + FOTG210_DMISGR1); in fotg210_enable_fifo_int()
55 u32 value = ioread32(fotg210->reg + FOTG210_DCFESR); in fotg210_set_cxdone() local
57 value |= DCFESR_CX_DONE; in fotg210_set_cxdone()
[all …]
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| /drivers/mmc/host/ |
| D | sdhci-of-esdhc.c | 49 int spec_reg, u32 value) in esdhc_readl_fixup() argument
63 if ((spec_reg == SDHCI_CAPABILITIES) && (value & SDHCI_CAN_DO_ADMA1)) { in esdhc_readl_fixup()
65 ret = value | SDHCI_CAN_DO_ADMA2; in esdhc_readl_fixup()
77 ret = value & 0x000fffff; in esdhc_readl_fixup()
78 ret |= (value >> 4) & SDHCI_DATA_LVL_MASK; in esdhc_readl_fixup()
79 ret |= (value << 1) & SDHCI_CMD_LVL; in esdhc_readl_fixup()
83 ret = value; in esdhc_readl_fixup()
88 int spec_reg, u32 value) in esdhc_readw_fixup() argument
94 ret = value & 0xffff; in esdhc_readw_fixup()
96 ret = (value >> shift) & 0xffff; in esdhc_readw_fixup()
[all …]
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| /drivers/staging/lustre/include/linux/libcfs/ |
| D | libcfs_fail.h | 42 int __cfs_fail_check_set(__u32 id, __u32 value, int set);
43 int __cfs_fail_timeout_set(__u32 id, __u32 value, int ms, int set);
79 static inline int cfs_fail_check_set(__u32 id, __u32 value, in cfs_fail_check_set() argument
85 ret = __cfs_fail_check_set(id, value, set); in cfs_fail_check_set()
89 id, value); in cfs_fail_check_set()
92 id, value); in cfs_fail_check_set()
108 #define CFS_FAIL_CHECK_VALUE(id, value) \ argument
109 cfs_fail_check_set(id, value, CFS_FAIL_LOC_VALUE, 0)
110 #define CFS_FAIL_CHECK_VALUE_QUIET(id, value) \ argument
111 cfs_fail_check_set(id, value, CFS_FAIL_LOC_VALUE, 1)
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| /drivers/pwm/ |
| D | pwm-bcm-iproc.c | 59 u32 value; in iproc_pwmc_enable() local
61 value = readl(ip->base + IPROC_PWM_CTRL_OFFSET); in iproc_pwmc_enable()
62 value |= 1 << IPROC_PWM_CTRL_EN_SHIFT(channel); in iproc_pwmc_enable()
63 writel(value, ip->base + IPROC_PWM_CTRL_OFFSET); in iproc_pwmc_enable()
71 u32 value; in iproc_pwmc_disable() local
73 value = readl(ip->base + IPROC_PWM_CTRL_OFFSET); in iproc_pwmc_disable()
74 value &= ~(1 << IPROC_PWM_CTRL_EN_SHIFT(channel)); in iproc_pwmc_disable()
75 writel(value, ip->base + IPROC_PWM_CTRL_OFFSET); in iproc_pwmc_disable()
86 u32 value, prescale; in iproc_pwmc_get_state() local
90 value = readl(ip->base + IPROC_PWM_CTRL_OFFSET); in iproc_pwmc_get_state()
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| /drivers/staging/sm750fb/ |
| D | ddk750_hwi2c.c | 15 unsigned int value; in sm750_hw_i2c_init() local
18 value = PEEK32(GPIO_MUX); in sm750_hw_i2c_init()
20 value |= (GPIO_MUX_30 | GPIO_MUX_31); in sm750_hw_i2c_init()
21 POKE32(GPIO_MUX, value); in sm750_hw_i2c_init()
29 value = PEEK32(I2C_CTRL) & ~(I2C_CTRL_MODE | I2C_CTRL_EN); in sm750_hw_i2c_init()
31 value |= I2C_CTRL_MODE; in sm750_hw_i2c_init()
32 value |= I2C_CTRL_EN; in sm750_hw_i2c_init()
33 POKE32(I2C_CTRL, value); in sm750_hw_i2c_init()
40 unsigned int value; in sm750_hw_i2c_close() local
43 value = PEEK32(I2C_CTRL) & ~I2C_CTRL_EN; in sm750_hw_i2c_close()
[all …]
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| /drivers/net/wireless/broadcom/b43/ |
| D | tables_phy_ht.c | 621 u32 type, value; in b43_httab_read() local
630 value = b43_phy_read(dev, B43_PHY_HT_TABLE_DATALO) & 0xFF; in b43_httab_read()
634 value = b43_phy_read(dev, B43_PHY_HT_TABLE_DATALO); in b43_httab_read()
638 value = b43_phy_read(dev, B43_PHY_HT_TABLE_DATAHI); in b43_httab_read()
639 value <<= 16; in b43_httab_read()
640 value |= b43_phy_read(dev, B43_PHY_HT_TABLE_DATALO); in b43_httab_read()
644 value = 0; in b43_httab_read()
647 return value; in b43_httab_read()
685 void b43_httab_write(struct b43_wldev *dev, u32 offset, u32 value) in b43_httab_write() argument
694 B43_WARN_ON(value & ~0xFF); in b43_httab_write()
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| /drivers/hid/ |
| D | hid-lg4ff.c | 284 static s32 lg4ff_adjust_dfp_x_axis(s32 value, u16 range) in lg4ff_adjust_dfp_x_axis() argument
290 return value; in lg4ff_adjust_dfp_x_axis()
292 return value; in lg4ff_adjust_dfp_x_axis()
298 new_value = 8192 + mult_frac(value - 8192, max_range, range); in lg4ff_adjust_dfp_x_axis()
308 struct hid_usage *usage, s32 value, struct lg_drv_data *drv_data) in lg4ff_adjust_input_event() argument
322 new_value = lg4ff_adjust_dfp_x_axis(value, entry->wdata.range); in lg4ff_adjust_input_event()
418 s32 *value; in lg4ff_play() local
432 value = entry->report->field[0]->value; in lg4ff_play()
444 value[0] = 0x13; in lg4ff_play()
445 value[1] = 0x00; in lg4ff_play()
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| /drivers/xen/xen-pciback/ |
| D | conf_space_header.c | 24 #define is_enable_cmd(value) ((value)&(PCI_COMMAND_MEMORY|PCI_COMMAND_IO)) argument
25 #define is_master_cmd(value) ((value)&PCI_COMMAND_MASTER) argument
49 static int command_read(struct pci_dev *dev, int offset, u16 *value, void *data) in command_read() argument
51 int ret = pci_read_config_word(dev, offset, value); in command_read()
54 *value &= PCI_COMMAND_GUEST; in command_read()
55 *value |= cmd->val & ~PCI_COMMAND_GUEST; in command_read()
60 static int command_write(struct pci_dev *dev, int offset, u16 value, void *data) in command_write() argument
68 if (!pci_is_enabled(dev) && is_enable_cmd(value)) { in command_write()
77 } else if (pci_is_enabled(dev) && !is_enable_cmd(value)) { in command_write()
86 if (!dev->is_busmaster && is_master_cmd(value)) { in command_write()
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