Searched full:ahb (Results 1 – 25 of 66) sorted by relevance
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| /Documentation/devicetree/bindings/arm/tegra/ |
| D | nvidia,tegra20-ahb.txt | 1 NVIDIA Tegra AHB
4 - compatible : For Tegra20, must contain "nvidia,tegra20-ahb". For
5 Tegra30, must contain "nvidia,tegra30-ahb". Otherwise, must contain
6 '"nvidia,<chip>-ahb", "nvidia,tegra30-ahb"' where <chip> is tegra124,
14 ahb: ahb@6000c004 {
15 compatible = "nvidia,tegra20-ahb";
16 reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
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| /Documentation/devicetree/bindings/clock/ |
| D | nspire-clock.txt | 5 "lsi,nspire-cx-ahb-divider" for the AHB divider in the CX model
6 "lsi,nspire-classic-ahb-divider" for the AHB divider in the older model
14 - clocks: For the "nspire-*-ahb-divider" compatible clocks, this is the parent
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| D | sunxi.txt | 24 "allwinner,sun4i-a10-ahb-clk" - for the AHB clock
25 "allwinner,sun5i-a13-ahb-clk" - for the AHB clock on A13
26 "allwinner,sun9i-a80-ahb-clk" - for the AHB bus clocks on A80
27 "allwinner,sun4i-a10-ahb-gates-clk" - for the AHB gates on A10
28 "allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13
29 "allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s
30 "allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20
218 clock-names = "ahb";
220 reset-names = "ahb";
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| D | qca,ath79-pll.txt | 3 The PPL controller provides the 3 main clocks of the SoC: CPU, DDR and AHB.
20 - clock-output-names: should be "cpu", "ddr", "ahb"
32 clock-output-names = "cpu", "ddr", "ahb";
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| /Documentation/devicetree/bindings/iommu/ |
| D | nvidia,tegra30-smmu.txt | 10 - nvidia,ahb : phandle to the ahb bus connected to SMMU.
20 nvidia,ahb = <&ahb>;
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| /Documentation/devicetree/bindings/misc/ |
| D | intel,ixp4xx-ahb-queue-manager.yaml | 5 $id: "http://devicetree.org/schemas/misc/intel,ixp4xx-ahb-queue-manager.yaml#"
8 title: Intel IXP4xx AHB Queue Manager
14 The IXP4xx AHB Queue Manager maintains queues as circular buffers in
26 - const: intel,ixp4xx-ahb-queue-manager
46 compatible = "intel,ixp4xx-ahb-queue-manager";
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| /Documentation/devicetree/bindings/dma/ |
| D | arm-pl08x.txt | 15 - lli-bus-interface-ahb1: if AHB master 1 is eligible for fetching LLIs
16 - lli-bus-interface-ahb2: if AHB master 2 is eligible for fetching LLIs
17 - mem-bus-interface-ahb1: if AHB master 1 is eligible for fetching memory contents
18 - mem-bus-interface-ahb2: if AHB master 2 is eligible for fetching memory contents
21 which AHB master that is used.
33 - dmas: List of DMA controller phandle, request channel and AHB master id
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| D | snps-dma.txt | 9 - dma-masters: Number of AHB masters supported by the controller
16 - data-width: Maximum data width supported by hardware per AHB master
21 - data_width: Maximum data width supported by hardware per AHB master
28 - snps,dma-protection-control: AHB HPROT[3:1] protection setting.
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| /Documentation/devicetree/bindings/pci/ |
| D | qcom,pcie.txt | 84 - "iface" Configuration AHB clock
117 - "ahb" AHB clock
124 - "iface" AHB clock
140 - "ahb" AHB reset
165 - "ahb" AHB reset
166 - "phy_ahb" PHY AHB reset
177 - "ahb" AHB Reset
189 - "ahb" AHB reset
268 reset-names = "axi", "ahb", "por", "pci", "phy";
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| /Documentation/devicetree/bindings/spi/ |
| D | spi-ath79.txt | 6 - clocks: phandle of the AHB clock.
7 - clock-names: has to be "ahb".
20 clock-names = "ahb";
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| D | allwinner,sun6i-a31-spi.yaml | 38 - const: ahb
87 clock-names = "ahb", "mod";
99 clock-names = "ahb", "mod";
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| D | qcom,spi-qcom-qspi.txt | 11 - clocks: Should contain the core and AHB clock.
12 - clock-names: Should be "core" for core clock and "iface" for AHB clock.
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| /Documentation/devicetree/bindings/watchdog/ |
| D | alphascale-asm9260.txt | 10 "ahb" - ahb gate.
29 clock-names = "mod", "ahb";
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| /Documentation/devicetree/bindings/soc/qcom/ |
| D | qcom,geni-se.txt | 13 - clock-names: Must contain "m-ahb" and "s-ahb".
14 - clocks: AHB clocks needed by the device.
63 clock-names = "m-ahb", "s-ahb";
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| /Documentation/devicetree/bindings/media/ |
| D | coda.txt | 17 - clocks : Should contain the ahb and per clocks, in the order
19 - clock-names : Should be "ahb", "per"
29 clock-names = "ahb", "per";
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| D | rockchip-rga.txt | 20 - reset-names: should be "core", "axi" and "ahb"
32 reset-names = "core, "axi", "ahb";
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| /Documentation/devicetree/bindings/crypto/ |
| D | allwinner,sun4i-a10-crypto.yaml | 40 - const: ahb
47 const: ahb
76 clock-names = "ahb", "mod";
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| /Documentation/devicetree/bindings/rtc/ |
| D | alphascale,asm9260-rtc.txt | 10 * "ahb" for the SoC RTC clock
17 clock-names = "ahb";
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| /Documentation/devicetree/bindings/display/rockchip/ |
| D | rockchip-vop.txt | 32 hclk_vop: for ahb bus to R/W the phy regs.
39 - ahb
56 reset-names = "axi", "ahb", "dclk";
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| /Documentation/devicetree/bindings/usb/ |
| D | ci-hdrc-usb2.txt | 40 - ahb-burst-config: it is vendor dependent, the required value should be
42 property is used to change AHB burst configuration, check the chipidea
49 "ahb-burst-config" is set to 0, if this property is missing the reset
55 "ahb-burst-config" is set to 0, if this property is missing the reset
112 ahb-burst-config = <0x0>;
132 ahb-burst-config = <0x0>;
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| D | allwinner,sun4i-a10-musb.txt | 8 - clocks : clock specifier for the musb controller ahb gate clock
9 - reset : reset specifier for the ahb reset (A31 and newer only)
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| /Documentation/devicetree/bindings/mmc/ |
| D | allwinner,sun4i-a10-mmc.yaml | 70 - const: ahb
79 const: ahb
94 clock-names = "ahb", "mmc";
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| /Documentation/devicetree/bindings/arm/stm32/ |
| D | mlahb.txt | 1 ML-AHB interconnect bindings
3 These bindings describe the STM32 SoCs ML-AHB interconnect bus which connects
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| /Documentation/devicetree/bindings/ata/ |
| D | qcom-sata.txt | 17 "slave_iface" - Fabric port AHB clock for SATA
18 "iface" - AHB clock
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| D | imx-sata.txt | 15 - clock-names : should include "sata", "sata_ref" and "ahb" entries
36 clock-names = "sata", "sata_ref", "ahb";
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