| /Documentation/devicetree/bindings/powerpc/fsl/ |
| D | l2cache.txt | 9 "fsl,8540-l2-cache-controller"
10 "fsl,8541-l2-cache-controller"
11 "fsl,8544-l2-cache-controller"
12 "fsl,8548-l2-cache-controller"
13 "fsl,8555-l2-cache-controller"
14 "fsl,8568-l2-cache-controller"
15 "fsl,b4420-l2-cache-controller"
16 "fsl,b4860-l2-cache-controller"
17 "fsl,bsc9131-l2-cache-controller"
18 "fsl,bsc9132-l2-cache-controller"
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| D | pmc.txt | 4 - compatible: "fsl,<chip>-pmc".
6 "fsl,mpc8349-pmc" should be listed for any chip whose PMC is
7 compatible. "fsl,mpc8313-pmc" should also be listed for any chip
10 "fsl,mpc8548-pmc" should be listed for any chip whose PMC is
11 compatible. "fsl,mpc8536-pmc" should also be listed for any chip
14 "fsl,mpc8641d-pmc" should be listed for any chip whose PMC is
15 compatible; all statements below that apply to "fsl,mpc8548-pmc" also
16 apply to "fsl,mpc8641d-pmc".
22 - reg: For devices compatible with "fsl,mpc8349-pmc", the first resource
26 For devices compatible with "fsl,mpc8548-pmc", the first resource
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| D | interlaken-lac.txt | 42 Definition: Must include "fsl,interlaken-lac". This represents only
54 "fsl,interlaken-lac-hv". This node represents the protected
58 - fsl,non-hv-node
59 Usage: required in "fsl,interlaken-lac-hv"
77 compatible = "fsl,interlaken-lac"
83 compatible = "fsl,interlaken-lac-hv"
85 fsl,non-hv-node = <&lac>;
113 Definition: Must include "fsl,interlaken-lac-portals"
134 Definition: Must include "fsl,interlaken-lac-portal-vX.Y" where X is
150 - fsl,liodn
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| D | mpc5121-psc.txt | 7 are specified by fsl,mpc5121-psc-uart nodes in the
8 fsl,mpc5121-immr SoC node. Additionally the PSC FIFO
9 Controller node fsl,mpc5121-psc-fifo is required there:
11 fsl,mpc512x-psc-uart nodes
15 - compatible : Should contain "fsl,<soc>-psc-uart" and "fsl,<soc>-psc"
23 - fsl,rx-fifo-size : the size of the RX fifo slice (a multiple of 4)
24 - fsl,tx-fifo-size : the size of the TX fifo slice (a multiple of 4)
30 for that is fsl,mpc5121-psc-spi. It requires a fsl,mpc5121-psc-fifo as well.
32 fsl,mpc5121-psc-uart nodes, just use spi instead of uart in the compatible
35 fsl,mpc512x-psc-fifo node
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| D | dma.txt | 9 - compatible : must include "fsl,elo-dma"
18 - compatible : must include "fsl,elo-dma-channel"
32 compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
39 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
46 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
53 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
60 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
75 - compatible : must include "fsl,eloplus-dma"
84 - compatible : must include "fsl,eloplus-dma-channel"
94 compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma";
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| D | mpc5200.txt | 21 "fsl,mpc5200-<device>".
29 compatible = "fsl,mpc5200b-<device>","fsl,mpc5200-<device>";
34 ie. ethernet on mpc5200: compatible = "fsl,mpc5200-fec";
35 ethernet on mpc5200b: compatible = "fsl,mpc5200b-fec", "fsl,mpc5200-fec";
39 "fsl,mpc5200-psc-i2s", not "fsl,mpc5200-i2s". This convention is chosen to
41 function. For example, "fsl,mpc5200-spi" and "fsl,mpc5200-psc-spi" describe
44 At the time of writing, exact chip may be either 'fsl,mpc5200' or
45 'fsl,mpc5200b'.
59 compatible mpc5200: "fsl,mpc5200-immr"
60 mpc5200b: "fsl,mpc5200b-immr"
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| D | pamu.txt | 12 "fsl,pamu-v1.0". The second is "fsl,pamu".
35 - fsl,portid-mapping : <u32>
48 connected to a specific PAMU device should have a "fsl,pamu-phandle" property
57 - fsl,primary-cache-geometry
63 - fsl,secondary-cache-geometry
76 - fsl,iommu-parent
83 - fsl,liodn-reg : <prop-encoded-array>
95 compatible = "fsl,pamu-v1.0", "fsl,pamu";
98 fsl,portid-mapping = <0xf80000>;
107 fsl,primary-cache-geometry = <32 1>;
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| /Documentation/devicetree/bindings/arm/ |
| D | fsl.yaml | 4 $id: http://devicetree.org/schemas/bindings/arm/fsl.yaml#
22 - fsl,imx1ads
23 - const: fsl,imx1
28 - fsl,imx23-evk
30 - const: fsl,imx23
35 - fsl,imx25-pdk
36 - const: fsl,imx25
41 - fsl,imx27-pdk
42 - const: fsl,imx27
47 - fsl,imx28-evk
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| /Documentation/devicetree/bindings/soc/fsl/cpm_qe/ |
| D | network.txt | 4 - fsl,cpm1-scc-enet
5 - fsl,cpm2-scc-enet
6 - fsl,cpm1-fec-enet
7 - fsl,cpm2-fcc-enet (third resource is GFEMR)
8 - fsl,qe-enet
13 compatible = "fsl,mpc8272-fcc-enet",
14 "fsl,cpm2-fcc-enet";
20 fsl,cpm-command = <12000300>;
26 fsl,pq1-fec-mdio (reg is same as first resource of FEC device)
27 fsl,cpm2-mdio-bitbang (reg is port C registers)
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| D | qe.txt | 16 - compatible : should be "fsl,qe";
20 - fsl,qe-num-riscs: define how many RISC engines the QE has.
21 - fsl,qe-snums: This property has to be specified as '/bits/ 8' value,
26 - fsl,firmware-phandle:
27 Usage: required only if there is no fsl,qe-firmware child node
32 "fsl,qe-firmware".
39 - fsl,qe-num-snums: define how many serial number(SNUM) the QE can use
40 for the threads. Use fsl,qe-snums instead to not only specify the
48 compatible = "fsl,qe";
53 fsl,qe-snums = /bits/ 8 <
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| /Documentation/devicetree/bindings/timer/ |
| D | fsl,imxgpt.txt | 7 - "fsl,imx1-gpt";
9 - "fsl,imx21-gpt";
11 - "fsl,imx27-gpt", "fsl,imx21-gpt";
13 - "fsl,imx31-gpt";
15 - "fsl,imx25-gpt", "fsl,imx31-gpt";
17 - "fsl,imx50-gpt", "fsl,imx31-gpt";
19 - "fsl,imx51-gpt", "fsl,imx31-gpt";
21 - "fsl,imx53-gpt", "fsl,imx31-gpt";
23 - "fsl,imx6q-gpt", "fsl,imx31-gpt";
25 - "fsl,imx6dl-gpt";
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| D | fsl,gtm.txt | 5 "fsl,<chip>-gtm", "fsl,gtm" for SOC GTMs
6 "fsl,<chip>-qe-gtm", "fsl,qe-gtm", "fsl,gtm" for QE GTMs
7 "fsl,<chip>-cpm2-gtm", "fsl,cpm2-gtm", "fsl,gtm" for CPM2 GTMs
15 compatible = "fsl,mpc8360-gtm", "fsl,gtm";
24 compatible = "fsl,mpc8360-qe-gtm", "fsl,qe-gtm", "fsl,gtm";
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| /Documentation/devicetree/bindings/rtc/ |
| D | rtc-fsl-ftm-alarm.txt | 4 - compatible : Should be "fsl,<chip>-ftm-alarm", the
6 "fsl,ls1012a-ftm-alarm"
7 "fsl,ls1021a-ftm-alarm"
8 "fsl,ls1028a-ftm-alarm"
9 "fsl,ls1043a-ftm-alarm"
10 "fsl,ls1046a-ftm-alarm"
11 "fsl,ls1088a-ftm-alarm"
12 "fsl,ls208xa-ftm-alarm"
13 "fsl,lx2160a-ftm-alarm"
17 - fsl,rcpm-wakeup property and rcpm node : Please refer
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| /Documentation/devicetree/bindings/memory-controllers/fsl/ |
| D | mmdc.txt | 6 - "fsl,imx6q-mmdc";
8 - "fsl,imx6qp-mmdc", "fsl,imx6q-mmdc";
10 - "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc";
12 - "fsl,imx6sll-mmdc", "fsl,imx6q-mmdc";
14 - "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc";
16 - "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc";
18 - "fsl,imx7ulp-mmdc", "fsl,imx6q-mmdc";
26 compatible = "fsl,imx6q-mmdc";
32 compatible = "fsl,imx6q-mmdc";
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| /Documentation/devicetree/bindings/mfd/ |
| D | mxs-lradc.txt | 4 - compatible: Should be "fsl,imx23-lradc" for i.MX23 SoC and "fsl,imx28-lradc"
10 - fsl,lradc-touchscreen-wires: Number of wires used to connect the touchscreen
14 - fsl,ave-ctrl: number of samples per direction to calculate an average value.
16 - fsl,ave-delay: delay between consecutive samples. Allowed value is
17 2 ... 2048. It is used if 'fsl,ave-ctrl' > 1, counts at
19 - fsl,settling: delay between plate switch to next sample. Allowed value is
26 compatible = "fsl,imx23-lradc";
29 fsl,lradc-touchscreen-wires = <4>;
30 fsl,ave-ctrl = <4>;
31 fsl,ave-delay = <2>;
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| /Documentation/devicetree/bindings/mmc/ |
| D | fsl-imx-esdhc.txt | 10 - compatible : Should be "fsl,<chip>-esdhc", the supported chips include
11 "fsl,imx25-esdhc"
12 "fsl,imx35-esdhc"
13 "fsl,imx51-esdhc"
14 "fsl,imx53-esdhc"
15 "fsl,imx6q-usdhc"
16 "fsl,imx6sl-usdhc"
17 "fsl,imx6sx-usdhc"
18 "fsl,imx6ull-usdhc"
19 "fsl,imx7d-usdhc"
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| D | fsl-esdhc.txt | 10 - compatible : should be "fsl,esdhc", or "fsl,<chip>-esdhc".
12 "fsl,mpc8536-esdhc"
13 "fsl,mpc8378-esdhc"
14 "fsl,p2020-esdhc"
15 "fsl,p4080-esdhc"
16 "fsl,t1040-esdhc"
17 "fsl,t4240-esdhc"
19 "fsl,ls1012a-esdhc"
20 "fsl,ls1028a-esdhc"
21 "fsl,ls1088a-esdhc"
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| /Documentation/devicetree/bindings/phy/ |
| D | mxs-usb-phy.txt | 5 * "fsl,imx23-usbphy" for imx23 and imx28
6 * "fsl,imx6q-usbphy" for imx6dq and imx6dl
7 * "fsl,imx6sl-usbphy" for imx6sl
8 * "fsl,vf610-usbphy" for Vybrid vf610
9 * "fsl,imx6sx-usbphy" for imx6sx
10 * "fsl,imx7ulp-usbphy" for imx7ulp
11 "fsl,imx23-usbphy" is still a fallback for other strings
14 - fsl,anatop: phandle for anatop register, it is only for imx6 SoC series
17 - fsl,tx-cal-45-dn-ohms: Integer [30-55]. Resistance (in ohms) of switchable
20 - fsl,tx-cal-45-dp-ohms: Integer [30-55]. Resistance (in ohms) of switchable
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| /Documentation/devicetree/bindings/clock/ |
| D | qoriq-clock.txt | 25 Chip-specific strings are of the form "fsl,<chip>-clockgen", such as:
26 * "fsl,p2041-clockgen"
27 * "fsl,p3041-clockgen"
28 * "fsl,p4080-clockgen"
29 * "fsl,p5020-clockgen"
30 * "fsl,p5040-clockgen"
31 * "fsl,t1023-clockgen"
32 * "fsl,t1024-clockgen"
33 * "fsl,t1040-clockgen"
34 * "fsl,t1042-clockgen"
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| /Documentation/devicetree/bindings/board/ |
| D | fsl-board.txt | 10 - compatible : Should be "fsl,<board>-bcsr"
16 compatible = "fsl,mpc8360mds-bcsr";
27 "fsl,<board>-fpga", "fsl,fpga-pixis", or
28 "fsl,<board>-fpga", "fsl,fpga-qixis"
37 compatible = "fsl,p1022ds-fpga", "fsl,fpga-ngpixis";
46 compatible = "fsl,ls2080ardb-fpga", "fsl,fpga-qixis";
56 - compatible : Should be "fsl,<board>-bcsr-gpio".
68 compatible = "fsl,mpc8360mds-bcsr";
74 compatible = "fsl,mpc8360mds-bcsr-gpio";
88 "fsl,<board>-fpga", "fsl,fpga-qixis-i2c"
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| /Documentation/devicetree/bindings/dma/ |
| D | fsl-imx-sdma.txt | 5 "fsl,imx25-sdma"
6 "fsl,imx31-sdma", "fsl,imx31-to1-sdma", "fsl,imx31-to2-sdma"
7 "fsl,imx35-sdma", "fsl,imx35-to1-sdma", "fsl,imx35-to2-sdma"
8 "fsl,imx51-sdma"
9 "fsl,imx53-sdma"
10 "fsl,imx6q-sdma"
11 "fsl,imx7d-sdma"
12 "fsl,imx8mq-sdma"
21 - fsl,sdma-ram-script-name : Should contain the full path of SDMA RAM
66 - fsl,sdma-event-remap : Register bits of sdma event remap, the format is
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| /Documentation/devicetree/bindings/ptp/ |
| D | ptp-qoriq.txt | 5 - compatible Should be "fsl,etsec-ptp" for eTSEC
6 Should be "fsl,fman-ptp-timer" for DPAA FMan
7 Should be "fsl,dpaa2-ptp" for DPAA2
8 Should be "fsl,enetc-ptp" for ENETC
15 - fsl,cksel Timer reference clock source.
16 - fsl,tclk-period Timer reference clock period in nanoseconds.
17 - fsl,tmr-prsc Prescaler, divides the output clock.
18 - fsl,tmr-add Frequency compensation value.
19 - fsl,tmr-fiper1 Fixed interval period pulse generator.
20 - fsl,tmr-fiper2 Fixed interval period pulse generator.
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| /Documentation/devicetree/bindings/soc/fsl/ |
| D | rcpm.txt | 8 - fsl,#rcpm-wakeup-cells : The number of IPPDEXPCR register cells in the
9 fsl,rcpm-wakeup property.
12 string. Chip-specific strings are of the form "fsl,<chip>-rcpm",
14 * "fsl,p2041-rcpm"
15 * "fsl,p5020-rcpm"
16 * "fsl,t4240-rcpm"
18 Chassis-version strings are of the form "fsl,qoriq-rcpm-<version>",
20 * "fsl,qoriq-rcpm-1.0": for chassis 1.0 rcpm
21 * "fsl,qoriq-rcpm-2.0": for chassis 2.0 rcpm
22 * "fsl,qoriq-rcpm-2.1": for chassis 2.1 rcpm
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| D | qman-portals.txt | 21 Definition: Must include "fsl,qman-portal-<hardware revision>"
22 May include "fsl,<SoC>-qman-portal" or "fsl,qman-portal"
36 - fsl,liodn
42 - fsl,iommu-parent
68 - fsl,liodn
73 - fsl,iommu-parent
95 compatible = "fsl,qman-portal-1.2.0", "fsl,qman-portal";
98 fsl,liodn = <1 2>;
99 fsl,qman-channel-id = <0>;
102 fsl,liodn = <0x21>;
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| /Documentation/devicetree/bindings/bus/ |
| D | imx-weim.txt | 12 "fsl,imx1-weim"
13 "fsl,imx27-weim"
14 "fsl,imx51-weim"
15 "fsl,imx50-weim"
16 "fsl,imx6q-weim"
29 - fsl,weim-cs-gpr: For "fsl,imx50-weim" and "fsl,imx6q-weim" type of
47 - fsl,burst-clk-enable For "fsl,imx50-weim" and "fsl,imx6q-weim" type of
53 - fsl,weim-cs-timing: The timing array, contains timing values for the
57 For i.MX1, i.MX21 ("fsl,imx1-weim") there are two
59 For i.MX25, i.MX27, i.MX31 and i.MX35 ("fsl,imx27-weim")
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