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Searched refs:BIT30 (Results 1 – 18 of 18) sorted by relevance

/drivers/staging/emxx_udc/
Demxx_udc.h86 #define BIT30 0x40000000 macro
258 #define EPN_BUF_TYPE BIT30
259 #define EPN_BUF_SINGLE BIT30
/drivers/net/wireless/realtek/rtlwifi/btcoexist/
Dhalbt_precomp.h61 #define BIT30 0x40000000 macro
/drivers/staging/rtl8192e/rtl8192e/
Dr8192E_hw.h133 #define RCR_ENCS2 BIT30
178 #define CAM_CM_SecCAMClr BIT30
Drtl_cam.c20 ulcommand |= BIT31|BIT30; in rtl92e_cam_reset()
/drivers/staging/rtl8723bs/include/
Dhal_com_reg.h774 #define IMR_BCNDMAINT5 BIT30 /* Beacon DMA Interrupt 5 */
822 #define PHIMR_TIMEOUT1 BIT30
873 #define UHIMR_TIMEOUT1 BIT30
934 #define IMR_TXCCK_88E BIT30 /* TXRPT interrupt when CCX bit of the packet is set */
1021 #define RCR_APP_MIC BIT30 /* MACRX will retain the MIC at the bottom of the packet. */
Drtl8723b_spec.h204 #define IMR_TIMER1_8723B BIT30 /* Timeout interrupt 1 */
Dosdep_service.h51 #define BIT30 0x40000000 macro
Dhal_intf.h277 #define RF_CHANGE_BY_HW BIT30
/drivers/staging/rtl8723bs/hal/
Dodm_debug.h85 #define ODM_COMP_COMMON BIT30
DHal8723BReg.h386 #define IMR_TIMER1_8723B BIT30 /* Timeout interrupt 1 */
Drtl8723b_phycfg.c853 PHY_SetBBReg(Adapter, rOFDM0_TxPseudoNoiseWgt, (BIT31|BIT30), 0x0); in phy_PostSetBwMode8723B()
Dodm_DIG.c161 if (value32 & BIT30) in odm_SearchPwdBLowerBound()
/drivers/staging/rtl8192e/
Drtl819x_Qos.h40 #define BIT30 0x40000000 macro
Drtllib.h1275 #define RF_CHANGE_BY_HW BIT30
/drivers/scsi/
Ddc395x.h46 #define BIT30 0x40000000 macro
/drivers/tty/
Dsynclinkmp.c5172 info->misc_ctrl_value |= BIT30; in init_adapter()
5183 info->misc_ctrl_value &= ~BIT30; in init_adapter()
Dsynclink.c5695 info->misc_ctrl_value |= BIT30; in usc_reset()
5706 info->misc_ctrl_value &= ~BIT30; in usc_reset()
/drivers/scsi/lpfc/
Dlpfc_hw4.h739 #define LPFC_SLI4_INTR30 BIT30