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Searched refs:dpm (Results 1 – 25 of 34) sorted by relevance

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/drivers/gpu/drm/amd/amdgpu/
Damdgpu_dpm.c109 if (rps == adev->pm.dpm.current_ps) in amdgpu_dpm_print_ps_status()
111 if (rps == adev->pm.dpm.requested_ps) in amdgpu_dpm_print_ps_status()
113 if (rps == adev->pm.dpm.boot_ps) in amdgpu_dpm_print_ps_status()
124 adev->pm.dpm.new_active_crtcs = 0; in amdgpu_dpm_get_active_displays()
125 adev->pm.dpm.new_active_crtc_count = 0; in amdgpu_dpm_get_active_displays()
131 adev->pm.dpm.new_active_crtcs |= (1 << amdgpu_crtc->crtc_id); in amdgpu_dpm_get_active_displays()
132 adev->pm.dpm.new_active_crtc_count++; in amdgpu_dpm_get_active_displays()
264 adev->pm.dpm.platform_caps = le32_to_cpu(power_info->pplib.ulPlatformCaps); in amdgpu_get_platform_caps()
265 adev->pm.dpm.backbias_response_time = le16_to_cpu(power_info->pplib.usBackbiasTime); in amdgpu_get_platform_caps()
266 adev->pm.dpm.voltage_response_time = le16_to_cpu(power_info->pplib.usVoltageTime); in amdgpu_get_platform_caps()
[all …]
Dsi_dpm.c1859 struct si_power_info *pi = adev->pm.dpm.priv; in si_get_pi()
1932 u32 p_limit1 = adev->pm.dpm.tdp_limit; in si_update_dte_from_pl2()
1933 u32 p_limit2 = adev->pm.dpm.near_tdp_limit; in si_update_dte_from_pl2()
1961 struct rv7xx_power_info *pi = adev->pm.dpm.priv; in rv770_get_pi()
1968 struct ni_power_info *pi = adev->pm.dpm.priv; in ni_get_pi()
2222 if (tdp_adjustment > (u32)adev->pm.dpm.tdp_od_limit) in si_calculate_adjusted_tdp_limits()
2225 max_tdp_limit = ((100 + 100) * adev->pm.dpm.tdp_limit) / 100; in si_calculate_adjusted_tdp_limits()
2228 *tdp_limit = ((100 + tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100; in si_calculate_adjusted_tdp_limits()
2229 *near_tdp_limit = adev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - adev->pm.dpm.tdp_limit); in si_calculate_adjusted_tdp_limits()
2231 *tdp_limit = ((100 - tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100; in si_calculate_adjusted_tdp_limits()
[all …]
Dkv_dpm.c76 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_convert_vid2_to_vid7()
98 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_convert_vid7_to_vid2()
379 struct kv_power_info *pi = adev->pm.dpm.priv; in kv_get_pi()
803 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_program_bootup_state()
905 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; in kv_populate_uvd_table()
978 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in kv_populate_vce_table()
1039 &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table; in kv_populate_samu_table()
1105 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; in kv_populate_acp_table()
1164 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_calculate_dfs_bypass_settings()
1231 adev->pm.dpm.current_ps = &pi->current_rps; in kv_update_current_ps()
[all …]
Damdgpu_pm.c166 pm = adev->pm.dpm.user_state; in amdgpu_get_dpm_state()
170 pm = adev->pm.dpm.user_state; in amdgpu_get_dpm_state()
200 adev->pm.dpm.user_state = state; in amdgpu_set_dpm_state()
206 adev->pm.dpm.user_state = state; in amdgpu_set_dpm_state()
298 level = adev->pm.dpm.forced_level; in amdgpu_get_dpm_forced_performance_level()
388 if (adev->pm.dpm.thermal_active) { in amdgpu_set_dpm_forced_performance_level()
397 adev->pm.dpm.forced_level = level; in amdgpu_set_dpm_forced_performance_level()
1164 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps; in amdgpu_set_pp_sclk_od()
1215 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps; in amdgpu_set_pp_mclk_od()
1518 temp = adev->pm.dpm.thermal.min_temp; in amdgpu_hwmon_show_temp_thresh()
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Damdgpu_drv.c265 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
266 module_param_named(dpm, amdgpu_dpm, int, 0444);
/drivers/gpu/drm/radeon/
Dr600_dpm.c147 if (rps == rdev->pm.dpm.current_ps) in r600_dpm_print_ps_status()
149 if (rps == rdev->pm.dpm.requested_ps) in r600_dpm_print_ps_status()
151 if (rps == rdev->pm.dpm.boot_ps) in r600_dpm_print_ps_status()
758 rdev->pm.dpm.thermal.min_temp = low_temp; in r600_set_thermal_temperature_range()
759 rdev->pm.dpm.thermal.max_temp = high_temp; in r600_set_thermal_temperature_range()
858 rdev->pm.dpm.platform_caps = le32_to_cpu(power_info->pplib.ulPlatformCaps); in r600_get_platform_caps()
859 rdev->pm.dpm.backbias_response_time = le16_to_cpu(power_info->pplib.usBackbiasTime); in r600_get_platform_caps()
860 rdev->pm.dpm.voltage_response_time = le16_to_cpu(power_info->pplib.usVoltageTime); in r600_get_platform_caps()
895 rdev->pm.dpm.fan.t_hyst = fan_info->fan.ucTHyst; in r600_parse_extended_power_table()
896 rdev->pm.dpm.fan.t_min = le16_to_cpu(fan_info->fan.usTMin); in r600_parse_extended_power_table()
[all …]
Dradeon_pm.c79 rdev->pm.dpm.ac_power = true; in radeon_pm_acpi_event_handler()
81 rdev->pm.dpm.ac_power = false; in radeon_pm_acpi_event_handler()
83 if (rdev->asic->dpm.enable_bapm) in radeon_pm_acpi_event_handler()
84 radeon_dpm_enable_bapm(rdev, rdev->pm.dpm.ac_power); in radeon_pm_acpi_event_handler()
473 enum radeon_pm_state_type pm = rdev->pm.dpm.user_state; in radeon_get_dpm_state()
490 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY; in radeon_set_dpm_state()
492 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED; in radeon_set_dpm_state()
494 rdev->pm.dpm.user_state = POWER_STATE_TYPE_PERFORMANCE; in radeon_set_dpm_state()
517 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level; in radeon_get_dpm_forced_performance_level()
554 if (rdev->asic->dpm.force_performance_level) { in radeon_set_dpm_forced_performance_level()
[all …]
Dbtc_dpm.c1232 return btc_find_valid_clock(&rdev->pm.dpm.dyn_state.valid_mclk_values, in btc_get_valid_mclk()
1239 return btc_find_valid_clock(&rdev->pm.dpm.dyn_state.valid_sclk_values, in btc_get_valid_sclk()
1282 if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > rdev->pm.dpm.dyn_state.mclk_sclk_ratio) in btc_adjust_clock_combinations()
1286 (rdev->pm.dpm.dyn_state.mclk_sclk_ratio - 1)) / in btc_adjust_clock_combinations()
1287 rdev->pm.dpm.dyn_state.mclk_sclk_ratio); in btc_adjust_clock_combinations()
1289 if ((pl->sclk - pl->mclk) > rdev->pm.dpm.dyn_state.sclk_mclk_delta) in btc_adjust_clock_combinations()
1293 rdev->pm.dpm.dyn_state.sclk_mclk_delta); in btc_adjust_clock_combinations()
1320 if ((*vddc - *vddci) > rdev->pm.dpm.dyn_state.vddc_vddci_delta) { in btc_apply_voltage_delta_rules()
1322 (*vddc - rdev->pm.dpm.dyn_state.vddc_vddci_delta)); in btc_apply_voltage_delta_rules()
1326 if ((*vddci - *vddc) > rdev->pm.dpm.dyn_state.vddc_vddci_delta) { in btc_apply_voltage_delta_rules()
[all …]
Dci_dpm.c198 struct ci_power_info *pi = rdev->pm.dpm.priv; in ci_get_pi()
283 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries == NULL) in ci_populate_bapm_vddc_vid_sidd()
285 if (rdev->pm.dpm.dyn_state.cac_leakage_table.count > 8) in ci_populate_bapm_vddc_vid_sidd()
287 if (rdev->pm.dpm.dyn_state.cac_leakage_table.count != in ci_populate_bapm_vddc_vid_sidd()
288 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count) in ci_populate_bapm_vddc_vid_sidd()
291 for (i = 0; i < rdev->pm.dpm.dyn_state.cac_leakage_table.count; i++) { in ci_populate_bapm_vddc_vid_sidd()
292 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) { in ci_populate_bapm_vddc_vid_sidd()
293 lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1); in ci_populate_bapm_vddc_vid_sidd()
294 hi_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2); in ci_populate_bapm_vddc_vid_sidd()
295 hi2_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3); in ci_populate_bapm_vddc_vid_sidd()
[all …]
Dsi_dpm.c1767 struct si_power_info *pi = rdev->pm.dpm.priv; in si_get_pi()
1841 u32 p_limit1 = rdev->pm.dpm.tdp_limit; in si_update_dte_from_pl2()
1842 u32 p_limit2 = rdev->pm.dpm.near_tdp_limit; in si_update_dte_from_pl2()
2132 if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit) in si_calculate_adjusted_tdp_limits()
2135 max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100; in si_calculate_adjusted_tdp_limits()
2138 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; in si_calculate_adjusted_tdp_limits()
2139 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit); in si_calculate_adjusted_tdp_limits()
2141 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; in si_calculate_adjusted_tdp_limits()
2142 adjustment_delta = rdev->pm.dpm.tdp_limit - *tdp_limit; in si_calculate_adjusted_tdp_limits()
2143 if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted) in si_calculate_adjusted_tdp_limits()
[all …]
Drv6xx_dpm.c45 struct rv6xx_power_info *pi = rdev->pm.dpm.priv; in rv6xx_get_pi()
921 rdev->pm.dpm.voltage_response_time, in rv6xx_program_voltage_timing_parameters()
925 rdev->pm.dpm.backbias_response_time, in rv6xx_program_voltage_timing_parameters()
1185 if (rdev->pm.dpm.new_active_crtcs & 1) { in rv6xx_program_display_gap()
1188 } else if (rdev->pm.dpm.new_active_crtcs & 2) { in rv6xx_program_display_gap()
1298 msleep((rdev->pm.dpm.voltage_response_time + 999) / 1000); in rv6xx_step_sw_voltage()
1548 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; in rv6xx_dpm_enable()
1553 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS) in rv6xx_dpm_enable()
1615 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; in rv6xx_dpm_disable()
1633 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS) in rv6xx_dpm_disable()
[all …]
Dkv_dpm.c253 struct kv_power_info *pi = rdev->pm.dpm.priv; in kv_get_pi()
558 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_convert_vid2_to_vid7()
580 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_convert_vid7_to_vid2()
721 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_program_bootup_state()
823 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; in kv_populate_uvd_table()
896 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in kv_populate_vce_table()
957 &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table; in kv_populate_samu_table()
1023 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; in kv_populate_acp_table()
1082 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_calculate_dfs_bypass_settings()
1282 kv_update_current_ps(rdev, rdev->pm.dpm.boot_ps); in kv_dpm_enable()
[all …]
Dni_dpm.c730 struct ni_power_info *pi = rdev->pm.dpm.priv; in ni_get_pi()
797 if ((rdev->pm.dpm.new_active_crtc_count > 1) || in ni_apply_state_adjust_rules()
803 if (rdev->pm.dpm.ac_power) in ni_apply_state_adjust_rules()
804 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in ni_apply_state_adjust_rules()
806 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; in ni_apply_state_adjust_rules()
808 if (rdev->pm.dpm.ac_power == false) { in ni_apply_state_adjust_rules()
875 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in ni_apply_state_adjust_rules()
878 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, in ni_apply_state_adjust_rules()
881 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in ni_apply_state_adjust_rules()
884 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk, in ni_apply_state_adjust_rules()
[all …]
Drs780_dpm.c45 struct igp_power_info *pi = rdev->pm.dpm.priv; in rs780_get_pi()
382 struct igp_ps *current_state = rs780_get_ps(rdev->pm.dpm.current_ps); in rs780_force_voltage()
409 struct igp_ps *current_state = rs780_get_ps(rdev->pm.dpm.current_ps); in rs780_force_fbdiv()
602 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; in rs780_dpm_enable()
654 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps; in rs780_dpm_set_power_state()
655 struct radeon_ps *old_ps = rdev->pm.dpm.current_ps; in rs780_dpm_set_power_state()
744 rdev->pm.dpm.boot_ps = rps; in rs780_parse_pplib_non_clock_info()
746 rdev->pm.dpm.uvd_ps = rps; in rs780_parse_pplib_non_clock_info()
809 rdev->pm.dpm.ps = kcalloc(power_info->pplib.ucNumStates, in rs780_parse_power_table()
812 if (!rdev->pm.dpm.ps) in rs780_parse_power_table()
[all …]
Dtrinity_dpm.c358 struct trinity_power_info *pi = rdev->pm.dpm.priv; in trinity_get_pi()
1062 rdev->pm.dpm.thermal.min_temp = low_temp; in trinity_set_thermal_temperature_range()
1063 rdev->pm.dpm.thermal.max_temp = high_temp; in trinity_set_thermal_temperature_range()
1125 trinity_update_current_ps(rdev, rdev->pm.dpm.boot_ps); in trinity_dpm_enable()
1173 trinity_update_current_ps(rdev, rdev->pm.dpm.boot_ps); in trinity_dpm_disable()
1228 rdev->pm.dpm.forced_level = level; in trinity_dpm_force_performance_level()
1236 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps; in trinity_dpm_pre_set_power_state()
1257 trinity_dpm_bapm_enable(rdev, rdev->pm.dpm.ac_power); in trinity_dpm_set_power_state()
1511 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in trinity_get_vce_clock_voltage()
1548 u32 num_active_displays = rdev->pm.dpm.new_active_crtc_count; in trinity_apply_state_adjust_rules()
[all …]
Drv770_dpm.c56 struct rv7xx_power_info *pi = rdev->pm.dpm.priv; in rv770_get_pi()
63 struct evergreen_power_info *pi = rdev->pm.dpm.priv; in evergreen_get_pi()
1190 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) { in rv770_init_smc_table()
1193 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_DONT_WAIT_FOR_VBLANK_ON_ALERT) in rv770_init_smc_table()
1196 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_GOTO_BOOT_ON_ALERT) in rv770_init_smc_table()
1200 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) in rv770_init_smc_table()
1346 if (rdev->pm.dpm.new_active_crtcs & 1) { in rv770_program_display_gap()
1349 } else if (rdev->pm.dpm.new_active_crtcs & 2) { in rv770_program_display_gap()
1498 rdev->pm.dpm.forced_level = level; in rv770_dpm_force_performance_level()
1707 voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time; in rv770_program_response_times()
[all …]
Dcypress_dpm.c1636 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) in cypress_init_smc_table()
1639 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) in cypress_init_smc_table()
1642 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) in cypress_init_smc_table()
1749 if (rdev->pm.dpm.new_active_crtc_count > 0) in cypress_program_display_gap()
1754 if (rdev->pm.dpm.new_active_crtc_count > 1) in cypress_program_display_gap()
1764 if ((rdev->pm.dpm.new_active_crtc_count > 0) && in cypress_program_display_gap()
1765 (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) { in cypress_program_display_gap()
1768 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) in cypress_program_display_gap()
1781 cypress_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0); in cypress_program_display_gap()
1808 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; in cypress_dpm_enable()
[all …]
Dsumo_dpm.c83 struct sumo_power_info *pi = rdev->pm.dpm.priv; in sumo_get_pi()
1174 rdev->pm.dpm.thermal.min_temp = low_temp; in sumo_set_thermal_temperature_range()
1175 rdev->pm.dpm.thermal.max_temp = high_temp; in sumo_set_thermal_temperature_range()
1232 sumo_update_current_ps(rdev, rdev->pm.dpm.boot_ps); in sumo_dpm_enable()
1277 sumo_update_current_ps(rdev, rdev->pm.dpm.boot_ps); in sumo_dpm_disable()
1283 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps; in sumo_dpm_pre_set_power_state()
1422 rdev->pm.dpm.boot_ps = rps; in sumo_parse_pplib_non_clock_info()
1426 rdev->pm.dpm.uvd_ps = rps; in sumo_parse_pplib_non_clock_info()
1484 rdev->pm.dpm.ps = kcalloc(state_array->ucNumEntries, in sumo_parse_power_table()
1487 if (!rdev->pm.dpm.ps) in sumo_parse_power_table()
[all …]
Dradeon.h1649 struct radeon_dpm dpm; member
1990 } dpm; member
2770 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2771 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2772 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
2773 #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
2774 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
2775 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
2776 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
2777 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
[all …]
Dradeon_uvd.c877 radeon_uvd_count_handles(rdev, &rdev->pm.dpm.sd, in radeon_uvd_idle_work_handler()
878 &rdev->pm.dpm.hd); in radeon_uvd_idle_work_handler()
899 if ((rdev->pm.dpm.sd != sd) || in radeon_uvd_note_usage()
900 (rdev->pm.dpm.hd != hd)) { in radeon_uvd_note_usage()
901 rdev->pm.dpm.sd = sd; in radeon_uvd_note_usage()
902 rdev->pm.dpm.hd = hd; in radeon_uvd_note_usage()
Dradeon_asic.c1085 .dpm = {
1178 .dpm = {
1284 .dpm = {
1404 .dpm = {
1498 .dpm = {
1591 .dpm = {
1739 .dpm = {
1860 .dpm = {
1998 .dpm = {
2168 .dpm = {
[all …]
Dradeon_drv.c264 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
265 module_param_named(dpm, radeon_dpm, int, 0444);
/drivers/net/can/
Djanz-ican3.c228 void __iomem *dpm; member
315 peer = ioread8(mod->dpm + MSYNC_PEER); in ican3_old_recv_msg()
316 locl = ioread8(mod->dpm + MSYNC_LOCL); in ican3_old_recv_msg()
333 memcpy_fromio(msg, mod->dpm, sizeof(*msg)); in ican3_old_recv_msg()
342 iowrite8(locl, mod->dpm + MSYNC_LOCL); in ican3_old_recv_msg()
360 peer = ioread8(mod->dpm + MSYNC_PEER); in ican3_old_send_msg()
361 locl = ioread8(mod->dpm + MSYNC_LOCL); in ican3_old_send_msg()
375 memcpy_toio(mod->dpm, msg, sizeof(*msg)); in ican3_old_send_msg()
382 iowrite8(locl, mod->dpm + MSYNC_LOCL); in ican3_old_send_msg()
405 dst = mod->dpm; in ican3_init_new_host_interface()
[all …]
/drivers/gpu/drm/amd/powerplay/hwmgr/
Dhardwaremanager.c249 adev->pm.dpm.thermal.min_temp = range.min; in phm_start_thermal_controller()
250 adev->pm.dpm.thermal.max_temp = range.max; in phm_start_thermal_controller()
251 adev->pm.dpm.thermal.max_edge_emergency_temp = range.edge_emergency_max; in phm_start_thermal_controller()
252 adev->pm.dpm.thermal.min_hotspot_temp = range.hotspot_min; in phm_start_thermal_controller()
253 adev->pm.dpm.thermal.max_hotspot_crit_temp = range.hotspot_crit_max; in phm_start_thermal_controller()
254 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range.hotspot_emergency_max; in phm_start_thermal_controller()
255 adev->pm.dpm.thermal.min_mem_temp = range.mem_min; in phm_start_thermal_controller()
256 adev->pm.dpm.thermal.max_mem_crit_temp = range.mem_crit_max; in phm_start_thermal_controller()
257 adev->pm.dpm.thermal.max_mem_emergency_temp = range.mem_emergency_max; in phm_start_thermal_controller()
/drivers/gpu/drm/amd/powerplay/
Dsmu_v11_0.c1202 adev->pm.dpm.thermal.min_temp = range.min; in smu_v11_0_start_thermal_control()
1203 adev->pm.dpm.thermal.max_temp = range.max; in smu_v11_0_start_thermal_control()
1204 adev->pm.dpm.thermal.max_edge_emergency_temp = range.edge_emergency_max; in smu_v11_0_start_thermal_control()
1205 adev->pm.dpm.thermal.min_hotspot_temp = range.hotspot_min; in smu_v11_0_start_thermal_control()
1206 adev->pm.dpm.thermal.max_hotspot_crit_temp = range.hotspot_crit_max; in smu_v11_0_start_thermal_control()
1207 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range.hotspot_emergency_max; in smu_v11_0_start_thermal_control()
1208 adev->pm.dpm.thermal.min_mem_temp = range.mem_min; in smu_v11_0_start_thermal_control()
1209 adev->pm.dpm.thermal.max_mem_crit_temp = range.mem_crit_max; in smu_v11_0_start_thermal_control()
1210 adev->pm.dpm.thermal.max_mem_emergency_temp = range.mem_emergency_max; in smu_v11_0_start_thermal_control()

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