| /drivers/usb/renesas_usbhs/ |
| D | pipe.c | 33 char *usbhs_pipe_name(struct usbhs_pipe *pipe) in usbhs_pipe_name() argument
35 return usbhsp_pipe_name[usbhs_pipe_type(pipe)]; in usbhs_pipe_name()
50 static void usbhsp_pipectrl_set(struct usbhs_pipe *pipe, u16 mask, u16 val) in usbhsp_pipectrl_set() argument
52 struct usbhs_priv *priv = usbhs_pipe_to_priv(pipe); in usbhsp_pipectrl_set()
53 int offset = usbhsp_addr_offset(pipe); in usbhsp_pipectrl_set()
55 if (usbhs_pipe_is_dcp(pipe)) in usbhsp_pipectrl_set()
61 static u16 usbhsp_pipectrl_get(struct usbhs_pipe *pipe) in usbhsp_pipectrl_get() argument
63 struct usbhs_priv *priv = usbhs_pipe_to_priv(pipe); in usbhsp_pipectrl_get()
64 int offset = usbhsp_addr_offset(pipe); in usbhsp_pipectrl_get()
66 if (usbhs_pipe_is_dcp(pipe)) in usbhsp_pipectrl_get()
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| D | fifo.c | 17 #define usbhsf_fifo_is_busy(f) ((f)->pipe) /* see usbhs_pipe_select_fifo */
32 struct usbhs_priv *priv = usbhs_pipe_to_priv(pkt->pipe); in usbhsf_null_handle()
45 void usbhs_pkt_push(struct usbhs_pipe *pipe, struct usbhs_pkt *pkt, in usbhs_pkt_push() argument
50 struct usbhs_priv *priv = usbhs_pipe_to_priv(pipe); in usbhs_pkt_push()
62 if (!pipe->handler) { in usbhs_pkt_push()
64 pipe->handler = &usbhsf_null_handler; in usbhs_pkt_push()
67 list_move_tail(&pkt->node, &pipe->list); in usbhs_pkt_push()
74 pkt->pipe = pipe; in usbhs_pkt_push()
76 pkt->handler = pipe->handler; in usbhs_pkt_push()
92 struct usbhs_pkt *__usbhsf_pkt_get(struct usbhs_pipe *pipe) in __usbhsf_pkt_get() argument
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| D | pipe.h | 38 struct usbhs_pipe *pipe; member
50 ((i) < (info)->size) && ((pos) = (info)->pipe + (i)); \
67 char *usbhs_pipe_name(struct usbhs_pipe *pipe);
70 void usbhs_pipe_free(struct usbhs_pipe *pipe);
73 int usbhs_pipe_is_dir_in(struct usbhs_pipe *pipe);
74 int usbhs_pipe_is_dir_host(struct usbhs_pipe *pipe);
75 int usbhs_pipe_is_running(struct usbhs_pipe *pipe);
76 void usbhs_pipe_running(struct usbhs_pipe *pipe, int running);
81 int usbhs_pipe_get_maxpacket(struct usbhs_pipe *pipe);
82 void usbhs_pipe_clear(struct usbhs_pipe *pipe);
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| /drivers/gpu/drm/gma500/ |
| D | mdfld_dsi_output.h | 75 #define CHECK_PIPE(pipe) ({ \ argument
76 const typeof(pipe) __pipe = (pipe); \
80 #define CHECK_PIPE(pipe) (pipe) argument
86 #define REG_OFFSET(pipe) (CHECK_PIPE(pipe) * 0x400) argument
89 #define MIPI_DEVICE_READY_REG(pipe) (0xb000 + REG_OFFSET(pipe)) argument
90 #define MIPI_INTR_STAT_REG(pipe) (0xb004 + REG_OFFSET(pipe)) argument
91 #define MIPI_INTR_EN_REG(pipe) (0xb008 + REG_OFFSET(pipe)) argument
92 #define MIPI_DSI_FUNC_PRG_REG(pipe) (0xb00c + REG_OFFSET(pipe)) argument
93 #define MIPI_HS_TX_TIMEOUT_REG(pipe) (0xb010 + REG_OFFSET(pipe)) argument
94 #define MIPI_LP_RX_TIMEOUT_REG(pipe) (0xb014 + REG_OFFSET(pipe)) argument
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| D | mdfld_dsi_dpi.c | 37 int pipe);
39 static void mdfld_wait_for_HS_DATA_FIFO(struct drm_device *dev, u32 pipe) in mdfld_wait_for_HS_DATA_FIFO() argument
41 u32 gen_fifo_stat_reg = MIPI_GEN_FIFO_STAT_REG(pipe); in mdfld_wait_for_HS_DATA_FIFO()
57 static void mdfld_wait_for_HS_CTRL_FIFO(struct drm_device *dev, u32 pipe) in mdfld_wait_for_HS_CTRL_FIFO() argument
59 u32 gen_fifo_stat_reg = MIPI_GEN_FIFO_STAT_REG(pipe); in mdfld_wait_for_HS_CTRL_FIFO()
74 static void mdfld_wait_for_DPI_CTRL_FIFO(struct drm_device *dev, u32 pipe) in mdfld_wait_for_DPI_CTRL_FIFO() argument
76 u32 gen_fifo_stat_reg = MIPI_GEN_FIFO_STAT_REG(pipe); in mdfld_wait_for_DPI_CTRL_FIFO()
92 static void mdfld_wait_for_SPL_PKG_SENT(struct drm_device *dev, u32 pipe) in mdfld_wait_for_SPL_PKG_SENT() argument
94 u32 intr_stat_reg = MIPI_INTR_STAT_REG(pipe); in mdfld_wait_for_SPL_PKG_SENT()
113 int pipe) in dsi_set_device_ready_state() argument
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| D | psb_irq.c | 25 psb_pipestat(int pipe) in psb_pipestat() argument
27 if (pipe == 0) in psb_pipestat()
29 if (pipe == 1) in psb_pipestat()
31 if (pipe == 2) in psb_pipestat()
37 mid_pipe_event(int pipe) in mid_pipe_event() argument
39 if (pipe == 0) in mid_pipe_event()
41 if (pipe == 1) in mid_pipe_event()
43 if (pipe == 2) in mid_pipe_event()
49 mid_pipe_vsync(int pipe) in mid_pipe_vsync() argument
51 if (pipe == 0) in mid_pipe_vsync()
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| /drivers/gpu/drm/ |
| D | drm_simple_kms_helper.c | 38 struct drm_simple_display_pipe *pipe; in drm_simple_kms_crtc_mode_valid() local
40 pipe = container_of(crtc, struct drm_simple_display_pipe, crtc); in drm_simple_kms_crtc_mode_valid()
41 if (!pipe->funcs || !pipe->funcs->mode_valid) in drm_simple_kms_crtc_mode_valid()
45 return pipe->funcs->mode_valid(crtc, mode); in drm_simple_kms_crtc_mode_valid()
65 struct drm_simple_display_pipe *pipe; in drm_simple_kms_crtc_enable() local
67 pipe = container_of(crtc, struct drm_simple_display_pipe, crtc); in drm_simple_kms_crtc_enable()
68 if (!pipe->funcs || !pipe->funcs->enable) in drm_simple_kms_crtc_enable()
71 plane = &pipe->plane; in drm_simple_kms_crtc_enable()
72 pipe->funcs->enable(pipe, crtc->state, plane->state); in drm_simple_kms_crtc_enable()
78 struct drm_simple_display_pipe *pipe; in drm_simple_kms_crtc_disable() local
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| D | drm_vblank.c | 85 drm_get_last_vbltimestamp(struct drm_device *dev, unsigned int pipe,
97 static void store_vblank(struct drm_device *dev, unsigned int pipe, in store_vblank() argument
101 struct drm_vblank_crtc *vblank = &dev->vblank[pipe]; in store_vblank()
113 static u32 drm_max_vblank_count(struct drm_device *dev, unsigned int pipe) in drm_max_vblank_count() argument
115 struct drm_vblank_crtc *vblank = &dev->vblank[pipe]; in drm_max_vblank_count()
124 static u32 drm_vblank_no_hw_counter(struct drm_device *dev, unsigned int pipe) in drm_vblank_no_hw_counter() argument
126 WARN_ON_ONCE(drm_max_vblank_count(dev, pipe) != 0); in drm_vblank_no_hw_counter()
130 static u32 __get_vblank_counter(struct drm_device *dev, unsigned int pipe) in __get_vblank_counter() argument
133 struct drm_crtc *crtc = drm_crtc_from_index(dev, pipe); in __get_vblank_counter()
143 return dev->driver->get_vblank_counter(dev, pipe); in __get_vblank_counter()
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| /drivers/gpu/drm/arm/display/komeda/ |
| D | komeda_pipeline.c | 17 struct komeda_pipeline *pipe; in komeda_pipeline_add() local
25 if (size < sizeof(*pipe)) { in komeda_pipeline_add()
30 pipe = devm_kzalloc(mdev->dev, size, GFP_KERNEL); in komeda_pipeline_add()
31 if (!pipe) in komeda_pipeline_add()
34 pipe->mdev = mdev; in komeda_pipeline_add()
35 pipe->id = mdev->n_pipelines; in komeda_pipeline_add()
36 pipe->funcs = funcs; in komeda_pipeline_add()
38 mdev->pipelines[mdev->n_pipelines] = pipe; in komeda_pipeline_add()
41 return pipe; in komeda_pipeline_add()
45 struct komeda_pipeline *pipe) in komeda_pipeline_destroy() argument
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| /drivers/media/platform/vsp1/ |
| D | vsp1_pipe.c | 244 void vsp1_pipeline_reset(struct vsp1_pipeline *pipe) in vsp1_pipeline_reset() argument
249 if (pipe->brx) { in vsp1_pipeline_reset()
250 struct vsp1_brx *brx = to_brx(&pipe->brx->subdev); in vsp1_pipeline_reset()
256 for (i = 0; i < ARRAY_SIZE(pipe->inputs); ++i) in vsp1_pipeline_reset()
257 pipe->inputs[i] = NULL; in vsp1_pipeline_reset()
259 pipe->output = NULL; in vsp1_pipeline_reset()
261 list_for_each_entry(entity, &pipe->entities, list_pipe) in vsp1_pipeline_reset()
262 entity->pipe = NULL; in vsp1_pipeline_reset()
264 INIT_LIST_HEAD(&pipe->entities); in vsp1_pipeline_reset()
265 pipe->state = VSP1_PIPELINE_STOPPED; in vsp1_pipeline_reset()
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| D | vsp1_video.c | 186 static void vsp1_video_calculate_partition(struct vsp1_pipeline *pipe, in vsp1_video_calculate_partition() argument
199 format = vsp1_entity_get_pad_format(&pipe->output->entity, in vsp1_video_calculate_partition()
200 pipe->output->entity.config, in vsp1_video_calculate_partition()
204 if (pipe->partitions <= 1) { in vsp1_video_calculate_partition()
208 vsp1_pipeline_propagate_partition(pipe, partition, index, in vsp1_video_calculate_partition()
233 unsigned int partitions = pipe->partitions - 1; in vsp1_video_calculate_partition()
249 vsp1_pipeline_propagate_partition(pipe, partition, index, &window); in vsp1_video_calculate_partition()
252 static int vsp1_video_pipeline_setup_partitions(struct vsp1_pipeline *pipe) in vsp1_video_pipeline_setup_partitions() argument
254 struct vsp1_device *vsp1 = pipe->output->entity.vsp1; in vsp1_video_pipeline_setup_partitions()
264 format = vsp1_entity_get_pad_format(&pipe->output->entity, in vsp1_video_pipeline_setup_partitions()
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| D | vsp1_drm.c | 33 static void vsp1_du_pipeline_frame_end(struct vsp1_pipeline *pipe, in vsp1_du_pipeline_frame_end() argument
36 struct vsp1_drm_pipeline *drm_pipe = to_vsp1_drm_pipeline(pipe); in vsp1_du_pipeline_frame_end()
64 struct vsp1_pipeline *pipe, in vsp1_du_insert_uif() argument
116 struct vsp1_pipeline *pipe, in vsp1_du_pipeline_setup_rpf() argument
190 ret = vsp1_du_insert_uif(vsp1, pipe, uif, &rpf->entity, RWPF_PAD_SOURCE, in vsp1_du_pipeline_setup_rpf()
191 pipe->brx, brx_input); in vsp1_du_pipeline_setup_rpf()
198 ret = v4l2_subdev_call(&pipe->brx->subdev, pad, set_fmt, NULL, in vsp1_du_pipeline_setup_rpf()
205 format.format.code, BRX_NAME(pipe->brx), format.pad); in vsp1_du_pipeline_setup_rpf()
211 ret = v4l2_subdev_call(&pipe->brx->subdev, pad, set_selection, NULL, in vsp1_du_pipeline_setup_rpf()
218 BRX_NAME(pipe->brx), sel.pad); in vsp1_du_pipeline_setup_rpf()
[all …]
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| /drivers/gpu/drm/i915/display/ |
| D | intel_fifo_underrun.c | 58 enum pipe pipe; in ivb_can_enable_err_int() local
62 for_each_pipe(dev_priv, pipe) { in ivb_can_enable_err_int()
63 crtc = intel_get_crtc_for_pipe(dev_priv, pipe); in ivb_can_enable_err_int()
75 enum pipe pipe; in cpt_can_enable_serr_int() local
80 for_each_pipe(dev_priv, pipe) { in cpt_can_enable_serr_int()
81 crtc = intel_get_crtc_for_pipe(dev_priv, pipe); in cpt_can_enable_serr_int()
93 i915_reg_t reg = PIPESTAT(crtc->pipe); in i9xx_check_fifo_underruns()
101 enable_mask = i915_pipestat_enable_mask(dev_priv, crtc->pipe); in i9xx_check_fifo_underruns()
105 trace_intel_cpu_fifo_underrun(dev_priv, crtc->pipe); in i9xx_check_fifo_underruns()
106 DRM_ERROR("pipe %c underrun\n", pipe_name(crtc->pipe)); in i9xx_check_fifo_underruns()
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| D | intel_color.c | 142 enum pipe pipe = crtc->pipe; in ilk_update_pipe_csc() local
144 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), preoff[0]); in ilk_update_pipe_csc()
145 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), preoff[1]); in ilk_update_pipe_csc()
146 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), preoff[2]); in ilk_update_pipe_csc()
148 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff[0] << 16 | coeff[1]); in ilk_update_pipe_csc()
149 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), coeff[2] << 16); in ilk_update_pipe_csc()
151 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff[3] << 16 | coeff[4]); in ilk_update_pipe_csc()
152 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), coeff[5] << 16); in ilk_update_pipe_csc()
154 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), coeff[6] << 16 | coeff[7]); in ilk_update_pipe_csc()
155 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff[8] << 16); in ilk_update_pipe_csc()
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| D | intel_dpio_phy.c | 648 enum pipe pipe = intel_crtc->pipe; in chv_set_phy_signal_level() local
655 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); in chv_set_phy_signal_level()
659 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); in chv_set_phy_signal_level()
662 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); in chv_set_phy_signal_level()
666 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); in chv_set_phy_signal_level()
669 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch)); in chv_set_phy_signal_level()
672 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val); in chv_set_phy_signal_level()
675 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch)); in chv_set_phy_signal_level()
678 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val); in chv_set_phy_signal_level()
683 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i)); in chv_set_phy_signal_level()
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| D | intel_sprite.c | 152 pipe_name(crtc->pipe)); in intel_pipe_update_start()
207 enum pipe pipe = crtc->pipe; in intel_pipe_update_end() local
237 pipe_name(pipe), crtc->debug.start_vbl_count, in intel_pipe_update_end()
247 pipe_name(pipe), in intel_pipe_update_end()
364 enum pipe pipe = plane->pipe; in skl_program_scaler() local
401 I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id), in skl_program_scaler()
403 I915_WRITE_FW(SKL_PS_VPHASE(pipe, scaler_id), in skl_program_scaler()
405 I915_WRITE_FW(SKL_PS_HPHASE(pipe, scaler_id), in skl_program_scaler()
407 I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y); in skl_program_scaler()
408 I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id), (crtc_w << 16) | crtc_h); in skl_program_scaler()
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| D | intel_vdsc.c | 489 enum pipe pipe = crtc->pipe; in intel_configure_pps_for_dsc_encoder() local
520 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe), pps_val); in intel_configure_pps_for_dsc_encoder()
522 I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe), in intel_configure_pps_for_dsc_encoder()
539 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe), pps_val); in intel_configure_pps_for_dsc_encoder()
541 I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe), in intel_configure_pps_for_dsc_encoder()
559 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe), pps_val); in intel_configure_pps_for_dsc_encoder()
561 I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe), in intel_configure_pps_for_dsc_encoder()
579 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe), pps_val); in intel_configure_pps_for_dsc_encoder()
581 I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe), in intel_configure_pps_for_dsc_encoder()
599 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe), pps_val); in intel_configure_pps_for_dsc_encoder()
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| /drivers/gpu/drm/lima/ |
| D | lima_sched.c | 17 struct lima_sched_pipe *pipe; member
59 return f->pipe->base.name; in lima_fence_get_timeline_name()
83 static struct lima_fence *lima_fence_create(struct lima_sched_pipe *pipe) in lima_fence_create() argument
91 fence->pipe = pipe; in lima_fence_create()
92 dma_fence_init(&fence->base, &lima_fence_ops, &pipe->fence_lock, in lima_fence_create()
93 pipe->fence_context, ++pipe->fence_seqno); in lima_fence_create()
158 int lima_sched_context_init(struct lima_sched_pipe *pipe, in lima_sched_context_init() argument
162 struct drm_sched_rq *rq = pipe->base.sched_rq + DRM_SCHED_PRIORITY_NORMAL; in lima_sched_context_init()
167 void lima_sched_context_fini(struct lima_sched_pipe *pipe, in lima_sched_context_fini() argument
196 struct lima_sched_pipe *pipe = to_lima_pipe(job->sched); in lima_sched_run_job() local
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| D | lima_pp.c | 24 struct lima_sched_pipe *pipe = dev->pipe + lima_pipe_pp; in lima_pp_handle_irq() local
32 pipe->error = true; in lima_pp_handle_irq()
45 struct lima_sched_pipe *pipe = dev->pipe + lima_pipe_pp; in lima_pp_irq_handler() local
54 if (atomic_dec_and_test(&pipe->task)) in lima_pp_irq_handler()
55 lima_sched_pipe_task_done(pipe); in lima_pp_irq_handler()
66 struct lima_sched_pipe *pipe = dev->pipe + lima_pipe_pp; in lima_pp_bcast_irq_handler() local
70 if (!pipe->current_task) in lima_pp_bcast_irq_handler()
73 frame = pipe->current_task->frame; in lima_pp_bcast_irq_handler()
76 struct lima_ip *ip = pipe->processor[i]; in lima_pp_bcast_irq_handler()
79 if (pipe->done & (1 << i)) in lima_pp_bcast_irq_handler()
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| /drivers/platform/goldfish/ |
| D | goldfish_pipe.c | 221 static int goldfish_pipe_cmd_locked(struct goldfish_pipe *pipe, in goldfish_pipe_cmd_locked() argument
224 pipe->command_buffer->cmd = cmd; in goldfish_pipe_cmd_locked()
226 pipe->command_buffer->status = PIPE_ERROR_INVAL; in goldfish_pipe_cmd_locked()
227 writel(pipe->id, pipe->dev->base + PIPE_REG_CMD); in goldfish_pipe_cmd_locked()
228 return pipe->command_buffer->status; in goldfish_pipe_cmd_locked()
231 static int goldfish_pipe_cmd(struct goldfish_pipe *pipe, enum PipeCmdCode cmd) in goldfish_pipe_cmd() argument
235 if (mutex_lock_interruptible(&pipe->lock)) in goldfish_pipe_cmd()
237 status = goldfish_pipe_cmd_locked(pipe, cmd); in goldfish_pipe_cmd()
238 mutex_unlock(&pipe->lock); in goldfish_pipe_cmd()
340 static int transfer_max_buffers(struct goldfish_pipe *pipe, in transfer_max_buffers() argument
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| /drivers/staging/octeon-usb/ |
| D | octeon-hcd.c | 467 if (usb_pipeisoc(urb->pipe)) in octeon_free_temp_buffer()
553 struct cvmx_usb_pipe *pipe) in cvmx_usb_pipe_needs_split() argument
555 return pipe->device_speed != CVMX_USB_SPEED_HIGH && in cvmx_usb_pipe_needs_split()
566 static inline int cvmx_usb_get_data_pid(struct cvmx_usb_pipe *pipe) in cvmx_usb_get_data_pid() argument
568 if (pipe->pid_toggle) in cvmx_usb_get_data_pid()
1097 struct cvmx_usb_pipe *pipe; in cvmx_usb_open_pipe() local
1099 pipe = kzalloc(sizeof(*pipe), GFP_ATOMIC); in cvmx_usb_open_pipe()
1100 if (!pipe) in cvmx_usb_open_pipe()
1105 pipe->flags |= CVMX_USB_PIPE_FLAGS_NEED_PING; in cvmx_usb_open_pipe()
1106 pipe->device_addr = device_addr; in cvmx_usb_open_pipe()
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| /drivers/net/wireless/ath/ath10k/ |
| D | usb.c | 36 ath10k_usb_alloc_urb_from_pipe(struct ath10k_usb_pipe *pipe) in ath10k_usb_alloc_urb_from_pipe() argument
42 if (!pipe->ar_usb) in ath10k_usb_alloc_urb_from_pipe()
45 spin_lock_irqsave(&pipe->ar_usb->cs_lock, flags); in ath10k_usb_alloc_urb_from_pipe()
46 if (!list_empty(&pipe->urb_list_head)) { in ath10k_usb_alloc_urb_from_pipe()
47 urb_context = list_first_entry(&pipe->urb_list_head, in ath10k_usb_alloc_urb_from_pipe()
50 pipe->urb_cnt--; in ath10k_usb_alloc_urb_from_pipe()
52 spin_unlock_irqrestore(&pipe->ar_usb->cs_lock, flags); in ath10k_usb_alloc_urb_from_pipe()
57 static void ath10k_usb_free_urb_to_pipe(struct ath10k_usb_pipe *pipe, in ath10k_usb_free_urb_to_pipe() argument
63 if (!pipe->ar_usb) in ath10k_usb_free_urb_to_pipe()
66 spin_lock_irqsave(&pipe->ar_usb->cs_lock, flags); in ath10k_usb_free_urb_to_pipe()
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| /drivers/net/wireless/ath/ath6kl/ |
| D | usb.c | 79 struct ath6kl_usb_pipe *pipe; member
130 ath6kl_usb_alloc_urb_from_pipe(struct ath6kl_usb_pipe *pipe) in ath6kl_usb_alloc_urb_from_pipe() argument
136 if (!pipe->ar_usb) in ath6kl_usb_alloc_urb_from_pipe()
139 spin_lock_irqsave(&pipe->ar_usb->cs_lock, flags); in ath6kl_usb_alloc_urb_from_pipe()
140 if (!list_empty(&pipe->urb_list_head)) { in ath6kl_usb_alloc_urb_from_pipe()
142 list_first_entry(&pipe->urb_list_head, in ath6kl_usb_alloc_urb_from_pipe()
145 pipe->urb_cnt--; in ath6kl_usb_alloc_urb_from_pipe()
147 spin_unlock_irqrestore(&pipe->ar_usb->cs_lock, flags); in ath6kl_usb_alloc_urb_from_pipe()
152 static void ath6kl_usb_free_urb_to_pipe(struct ath6kl_usb_pipe *pipe, in ath6kl_usb_free_urb_to_pipe() argument
158 if (!pipe->ar_usb) in ath6kl_usb_free_urb_to_pipe()
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| /drivers/gpu/drm/i915/ |
| D | i915_reg.h | 228 #define _PIPE(pipe, a, b) _PICK_EVEN(pipe, a, b) argument
234 #define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b)) argument
242 #define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) argument
243 #define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) argument
251 #define _MMIO_PIPE2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->pipe_offsets[pipe] - \ argument
258 #define _CURSOR2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->cursor_offsets[(pipe)] - \ argument
1054 #define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL) argument
1132 #define _DP_SSC(val, pipe) ((val) << (2 * (pipe))) argument
1133 #define DP_SSC_MASK(pipe) _DP_SSC(0x3, (pipe)) argument
1134 #define DP_SSC_PWR_ON(pipe) _DP_SSC(0x0, (pipe)) argument
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| /drivers/rpmsg/ |
| D | qcom_glink_smem.c | 51 struct glink_smem_pipe *pipe = to_smem_pipe(np); in glink_smem_rx_avail() local
57 if (!pipe->fifo) { in glink_smem_rx_avail()
58 fifo = qcom_smem_get(pipe->remote_pid, in glink_smem_rx_avail()
66 pipe->fifo = fifo; in glink_smem_rx_avail()
67 pipe->native.length = len; in glink_smem_rx_avail()
70 head = le32_to_cpu(*pipe->head); in glink_smem_rx_avail()
71 tail = le32_to_cpu(*pipe->tail); in glink_smem_rx_avail()
74 return pipe->native.length - tail + head; in glink_smem_rx_avail()
82 struct glink_smem_pipe *pipe = to_smem_pipe(np); in glink_smem_rx_peak() local
86 tail = le32_to_cpu(*pipe->tail); in glink_smem_rx_peak()
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