| /Documentation/devicetree/bindings/spi/ |
| D | spi-dw.txt | 4 - compatible: should be "snps,designware-spi"
5 - #address-cells: see spi-bus.txt
6 - #size-cells: see spi-bus.txt
7 - reg: address and length of the spi master registers
8 - interrupts: should contain one interrupt
9 - clocks: spi clock phandle
10 - num-cs: see spi-bus.txt
13 - cs-gpios: see spi-bus.txt
18 compatible = "snps,designware-spi";
22 num-cs = <2>;
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| D | spi-fsl-dspi.txt | 4 - compatible : "fsl,vf610-dspi", "fsl,ls1021a-v1.0-dspi",
5 "fsl,ls2085a-dspi"
7 "fsl,ls2080a-dspi" followed by "fsl,ls2085a-dspi"
8 "fsl,ls1012a-dspi" followed by "fsl,ls1021a-v1.0-dspi"
9 "fsl,ls1088a-dspi" followed by "fsl,ls1021a-v1.0-dspi"
10 - reg : Offset and length of the register set for the device
11 - interrupts : Should contain SPI controller interrupt
12 - clocks: from common clock binding: handle to dspi clock.
13 - clock-names: from common clock binding: Shall be "dspi".
14 - pinctrl-0: pin control group to be used for this controller.
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| D | spi-lantiq-ssc.txt | 4 - compatible: "lantiq,ase-spi", "lantiq,falcon-spi", "lantiq,xrx100-spi"
5 - #address-cells: see spi-bus.txt
6 - #size-cells: see spi-bus.txt
7 - reg: address and length of the spi master registers
8 - interrupts: should contain the "spi_rx", "spi_tx" and "spi_err" interrupt.
12 - clocks: spi clock phandle
13 - num-cs: see spi-bus.txt, set to 8 if unset
14 - base-cs: the number of the first chip select, set to 1 if unset.
20 compatible = "lantiq,xrx200-spi", "lantiq,xrx100-spi";
22 interrupt-parent = <&icu0>;
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| D | omap-spi.txt | 4 - compatible :
5 - "ti,am654-mcspi" for AM654.
6 - "ti,omap2-mcspi" for OMAP2 & OMAP3.
7 - "ti,omap4-mcspi" for OMAP4+.
8 - ti,spi-num-cs : Number of chipselect supported by the instance.
9 - ti,hwmods: Name of the hwmod associated to the McSPI
10 - ti,pindir-d0-out-d1-in: Select the D0 pin as output and D1 as
15 - dmas: List of DMA specifiers with the controller specific format
18 - dma-names: List of DMA request names. These strings correspond
28 #address-cells = <1>;
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| D | spi-cadence.txt | 2 -------------------------------------------
5 - compatible : Should be "cdns,spi-r1p6" or "xlnx,zynq-spi-r1p6".
6 - reg : Physical base address and size of SPI registers map.
7 - interrupts : Property with a value describing the interrupt
9 - clock-names : List of input clock names - "ref_clk", "pclk"
11 - clocks : Clock phandles (see clock bindings for details).
14 - num-cs : Number of chip selects used.
17 - is-decoded-cs : Flag to indicate whether decoder is used or not.
22 compatible = "xlnx,zynq-spi-r1p6";
23 clock-names = "ref_clk", "pclk";
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| D | spi-bcm63xx.txt | 4 - compatible: must contain one of "brcm,bcm6348-spi", "brcm,bcm6358-spi".
5 - reg: Base address and size of the controllers memory area.
6 - interrupts: Interrupt for the SPI block.
7 - clocks: phandle of the SPI clock.
8 - clock-names: has to be "spi".
9 - #address-cells: <1>, as required by generic SPI binding.
10 - #size-cells: <0>, also as required by generic SPI binding.
13 - num-cs: some controllers have less than 8 cs signals. Defaults to 8
21 compatible = "brcm,bcm6368-spi", "brcm,bcm6358-spi";
27 clock-names = "spi";
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| D | spi-bcm63xx-hsspi.txt | 4 - compatible: must contain of "brcm,bcm6328-hsspi".
5 - reg: Base address and size of the controllers memory area.
6 - interrupts: Interrupt for the SPI block.
7 - clocks: phandles of the SPI clock and the PLL clock.
8 - clock-names: must be "hsspi", "pll".
9 - #address-cells: <1>, as required by generic SPI binding.
10 - #size-cells: <0>, also as required by generic SPI binding.
13 - num-cs: some controllers have less than 8 cs signals. Defaults to 8
21 compatible = "brcm,bcm6328-hsspi";
27 clock-names = "hsspi", "pll";
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| D | spi-armada-3700.txt | 5 - compatible: should be "marvell,armada-3700-spi"
6 - reg: physical base address of the controller and length of memory mapped
8 - interrupts: The interrupt number. The interrupt specifier format depends on
10 - clocks: Must contain the clock source, usually from the North Bridge clocks.
11 - num-cs: The number of chip selects that is supported by this SPI Controller
12 - #address-cells: should be 1.
13 - #size-cells: should be 0.
18 compatible = "marvell,armada-3700-spi";
19 #address-cells = <1>;
20 #size-cells = <0>;
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| D | spi-gpio.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SPI-GPIO devicetree bindings
10 - Rob Herring <robh@kernel.org>
13 This represents a group of 3-n GPIO lines used for bit-banged SPI on
17 - $ref: "/schemas/spi/spi-controller.yaml#"
21 const: spi-gpio
23 sck-gpios:
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| D | snps,dw-apb-ssi.txt | 4 - compatible : "snps,dw-apb-ssi" or "mscc,<soc>-spi", where soc is "ocelot" or
5 "jaguar2", or "amazon,alpine-dw-apb-ssi"
6 - reg : The register base for the controller. For "mscc,<soc>-spi", a second
8 - interrupts : One interrupt, used by the controller.
9 - #address-cells : <1>, as required by generic SPI binding.
10 - #size-cells : <0>, also as required by generic SPI binding.
11 - clocks : phandles for the clocks, see the description of clock-names below.
13 is optional. If a single clock is specified but no clock-name, it is the
17 - clock-names : Contains the names of the clocks:
20 - cs-gpios : Specifies the gpio pins to be used for chipselects.
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| D | spi-zynq-qspi.txt | 2 -------------------------------------------------------------------
5 - compatible : Should be "xlnx,zynq-qspi-1.0".
6 - reg : Physical base address and size of QSPI registers map.
7 - interrupts : Property with a value describing the interrupt
9 - clock-names : List of input clock names - "ref_clk", "pclk"
11 - clocks : Clock phandles (see clock bindings for details).
14 - num-cs : Number of chip selects used.
18 compatible = "xlnx,zynq-qspi-1.0";
20 interrupt-parent = <&intc>;
22 clock-names = "ref_clk", "pclk";
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| D | spi-zynqmp-qspi.txt | 2 -------------------------------------------------------------------
5 - compatible : Should be "xlnx,zynqmp-qspi-1.0".
6 - reg : Physical base address and size of GQSPI registers map.
7 - interrupts : Property with a value describing the interrupt
9 - clock-names : List of input clock names - "ref_clk", "pclk"
11 - clocks : Clock phandles (see clock bindings for details).
14 - num-cs : Number of chip selects used.
18 compatible = "xlnx,zynqmp-qspi-1.0";
19 clock-names = "ref_clk", "pclk";
22 interrupt-parent = <&gic>;
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| D | spi-rspi.txt | 4 - compatible : For Renesas Serial Peripheral Interface on legacy SH:
5 "renesas,rspi-<soctype>", "renesas,rspi" as fallback.
7 "renesas,rspi-<soctype>", "renesas,rspi-rz" as fallback.
8 For Quad Serial Peripheral Interface on R-Car Gen2 and
10 "renesas,qspi-<soctype>", "renesas,qspi" as fallback.
12 - "renesas,rspi-sh7757" (SH)
13 - "renesas,rspi-r7s72100" (RZ/A1H)
14 - "renesas,rspi-r7s9210" (RZ/A2)
15 - "renesas,qspi-r8a7743" (RZ/G1M)
16 - "renesas,qspi-r8a7744" (RZ/G1N)
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| D | spi-davinci.txt | 4 Keystone 2 - http://www.ti.com/lit/ug/sprugp2a/sprugp2a.pdf
5 dm644x - http://www.ti.com/lit/ug/sprue32a/sprue32a.pdf
6 OMAP-L138/da830 - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
9 - #address-cells: number of cells required to define a chip select
11 - #size-cells: should be zero.
12 - compatible:
13 - "ti,dm6441-spi" for SPI used similar to that on DM644x SoC family
14 - "ti,da830-spi" for SPI used similar to that on DA8xx SoC family
15 - "ti,keystone-spi" for SPI used similar to that on Keystone2 SoC
17 - reg: Offset and length of SPI controller register space
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| D | fsl-imx-cspi.txt | 5 - compatible :
6 - "fsl,imx1-cspi" for SPI compatible with the one integrated on i.MX1
7 - "fsl,imx21-cspi" for SPI compatible with the one integrated on i.MX21
8 - "fsl,imx27-cspi" for SPI compatible with the one integrated on i.MX27
9 - "fsl,imx31-cspi" for SPI compatible with the one integrated on i.MX31
10 - "fsl,imx35-cspi" for SPI compatible with the one integrated on i.MX35
11 - "fsl,imx51-ecspi" for SPI compatible with the one integrated on i.MX51
12 - "fsl,imx53-ecspi" for SPI compatible with the one integrated on i.MX53 and later Soc
13 - "fsl,imx8mq-ecspi" for SPI compatible with the one integrated on i.MX8M
14 - reg : Offset and length of the register set for the device
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| D | spi-samsung.txt | 8 - compatible: should be one of the following.
9 - samsung,s3c2443-spi: for s3c2443, s3c2416 and s3c2450 platforms
10 - samsung,s3c6410-spi: for s3c6410 platforms
11 - samsung,s5pv210-spi: for s5pv210 and s5pc110 platforms
12 - samsung,exynos5433-spi: for exynos5433 compatible controllers
13 - samsung,exynos7-spi: for exynos7 platforms <DEPRECATED>
15 - reg: physical base address of the controller and length of memory mapped
18 - interrupts: The interrupt number to the cpu. The interrupt specifier format
21 - dmas : Two or more DMA channel specifiers following the convention outlined
24 - dma-names: Names for the dma channels. There must be at least one channel
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| D | spi-controller.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Brown <broonie@kernel.org>
20 pattern: "^spi(@.*|-[0-9a-f])*$"
22 "#address-cells":
25 "#size-cells":
28 cs-gpios:
32 increased automatically with max(cs-gpios, hardware chip selects).
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| /Documentation/devicetree/bindings/memory-controllers/ |
| D | omap-gpmc.txt | 7 - compatible: Should be set to one of the following:
9 ti,omap2420-gpmc (omap2420)
10 ti,omap2430-gpmc (omap2430)
11 ti,omap3430-gpmc (omap3430 & omap3630)
12 ti,omap4430-gpmc (omap4430 & omap4460 & omap543x)
13 ti,am3352-gpmc (am335x devices)
15 - reg: A resource specifier for the register space
17 - ti,hwmods: Should be set to "ti,gpmc" until the DT transition is
19 - #address-cells: Must be set to 2 to allow memory address translation
20 - #size-cells: Must be set to 1 to allow CS address passing
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| /Documentation/devicetree/bindings/mtd/ |
| D | gpmc-onenand.txt | 7 explained in a separate documents - please refer to
8 Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
12 - compatible: "ti,omap2-onenand"
13 - reg: The CS line the peripheral is connected to
14 - gpmc,device-width: Width of the ONENAND device connected to the GPMC
19 - int-gpios: GPIO specifier for the INT pin.
23 - #address-cells: should be set to 1
24 - #size-cells: should be set to 1
29 compatible = "ti,omap3430-gpmc";
33 gpmc,num-cs = <8>;
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| D | gpmc-nor.txt | 8 Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
11 - bank-width: Width of NOR flash in bytes. GPMC supports 8-bit and
12 16-bit devices and so must be either 1 or 2 bytes.
13 - compatible: Documentation/devicetree/bindings/mtd/mtd-physmap.txt
14 - gpmc,cs-on-ns: Chip-select assertion time
15 - gpmc,cs-rd-off-ns: Chip-select de-assertion time for reads
16 - gpmc,cs-wr-off-ns: Chip-select de-assertion time for writes
17 - gpmc,oe-on-ns: Output-enable assertion time
18 - gpmc,oe-off-ns: Output-enable de-assertion time
19 - gpmc,we-on-ns Write-enable assertion time
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| D | gpmc-nand.txt | 7 explained in a separate documents - please refer to
8 Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
11 Documentation/devicetree/bindings/mtd/nand-controller.yaml
16 - compatible: "ti,omap2-nand"
17 - reg: range id (CS number), base offset and length of the
19 - interrupts: Two interrupt specifiers, one for fifoevent, one for termcount.
23 - nand-bus-width: Set this numeric value to 16 if the hardware
27 - ti,nand-ecc-opt: A string setting the ECC layout to use. One of:
28 "sw" 1-bit Hamming ecc code via software
30 "hw-romcode" <deprecated> use "ham1" instead
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| /Documentation/devicetree/bindings/leds/backlight/ |
| D | pm8941-wled.txt | 4 - compatible: should be "qcom,pm8941-wled"
5 - reg: slave address
8 - default-brightness: brightness value on boot, value from: 0-4095
10 - label: The name of the backlight device
11 - qcom,cs-out: bool; enable current sink output
12 - qcom,cabc: bool; enable content adaptive backlight control
13 - qcom,ext-gen: bool; use externally generated modulator signal to dim
14 - qcom,current-limit: mA; per-string current limit; value from 0 to 25
16 - qcom,current-boost-limit: mA; boost current limit; one of:
19 - qcom,switching-freq: kHz; switching frequency; one of:
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| /Documentation/devicetree/bindings/gpio/ |
| D | spear_spics.txt | 1 === ST Microelectronics SPEAr SPI CS Driver ===
17 * compatible: should be defined as "st,spear-spics-gpio"
19 * st-spics,peripcfg-reg: peripheral configuration register offset
20 * st-spics,sw-enable-bit: bit offset to enable sw control
21 * st-spics,cs-value-bit: bit offset to drive chipselect low or high
22 * st-spics,cs-enable-mask: chip select number bit mask
23 * st-spics,cs-enable-shift: chip select number program offset
24 * gpio-controller: Marks the device node as gpio controller
25 * #gpio-cells: should be 1 and will mention chip select number
30 -------
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| /Documentation/devicetree/bindings/net/ |
| D | gpmc-eth.txt | 4 General-Purpose Memory Controller can be used to connect Pseudo-SRAM devices
12 Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
18 Child nodes need to specify the GPMC bus address width using the "bank-width"
20 specify the I/O registers address width. Even when the GPMC has a maximum 16-bit
21 address width, it supports devices with 32-bit word registers.
23 OMAP2+ board, "bank-width = <2>;" and "reg-io-width = <4>;".
26 - bank-width: Address width of the device in bytes. GPMC supports 8-bit
27 and 16-bit devices and so must be either 1 or 2 bytes.
28 - compatible: Compatible string property for the ethernet child device.
29 - gpmc,cs-on-ns: Chip-select assertion time
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| /Documentation/devicetree/bindings/pci/ |
| D | nvidia,tegra20-pcie.txt | 4 - compatible: Must be:
5 - "nvidia,tegra20-pcie": for Tegra20
6 - "nvidia,tegra30-pcie": for Tegra30
7 - "nvidia,tegra124-pcie": for Tegra124 and Tegra132
8 - "nvidia,tegra210-pcie": for Tegra210
9 - "nvidia,tegra186-pcie": for Tegra186
10 - power-domains: To ungate power partition by BPMP powergate driver. Must
13 - device_type: Must be "pci"
14 - reg: A list of physical base address and length for each set of controller
15 registers. Must contain an entry for each entry in the reg-names property.
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