Searched +full:phy +full:- +full:device (Results 1 – 25 of 278) sorted by relevance
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| /Documentation/driver-api/phy/ |
| D | phy.rst | 2 PHY subsystem
7 This document explains the Generic PHY Framework along with the APIs provided,
8 and how-to-use.
13 *PHY* is the abbreviation for physical layer. It is used to connect a device
14 to the physical medium e.g., the USB controller has a PHY to provide functions
15 such as serialization, de-serialization, encoding, decoding and is responsible
17 controllers have PHY functionality embedded into it and others use an external
18 PHY. Other peripherals that use PHY include Wireless LAN, Ethernet,
21 The intention of creating this framework is to bring the PHY drivers spread
22 all over the Linux kernel to drivers/phy to increase code re-use and for
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| /Documentation/devicetree/bindings/phy/ |
| D | rcar-gen3-phy-usb2.txt | 1 * Renesas R-Car generation 3 USB 2.0 PHY
3 This file provides information on what the device node for the R-Car generation
4 3, RZ/G1C, RZ/G2 and RZ/A2 USB 2.0 PHY contain.
7 - compatible: "renesas,usb2-phy-r7s9210" if the device is a part of an R7S9210
9 "renesas,usb2-phy-r8a77470" if the device is a part of an R8A77470
11 "renesas,usb2-phy-r8a774a1" if the device is a part of an R8A774A1
13 "renesas,usb2-phy-r8a774c0" if the device is a part of an R8A774C0
15 "renesas,usb2-phy-r8a7795" if the device is a part of an R8A7795
17 "renesas,usb2-phy-r8a7796" if the device is a part of an R8A7796
19 "renesas,usb2-phy-r8a77965" if the device is a part of an
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| D | phy-hisi-inno-usb2.txt | 1 Device tree bindings for HiSilicon INNO USB2 PHY
4 - compatible: Should be one of the following strings:
5 "hisilicon,inno-usb2-phy",
6 "hisilicon,hi3798cv200-usb2-phy".
7 - reg: Should be the address space for PHY configuration register in peripheral
9 - clocks: The phandle and clock specifier pair for INNO USB2 PHY device
11 - resets: The phandle and reset specifier pair for INNO USB2 PHY device reset
13 - #address-cells: Must be 1.
14 - #size-cells: Must be 0.
16 The INNO USB2 PHY device should be a child node of peripheral controller that
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| D | phy-bindings.txt | 1 This document explains only the device tree data binding. For general
2 information about PHY subsystem refer to Documentation/driver-api/phy/phy.rst
4 PHY device node
8 #phy-cells: Number of cells in a PHY specifier; The meaning of all those
9 cells is defined by the binding for the phy node. The PHY
11 PHY.
14 phy-supply: Phandle to a regulator that provides power to the PHY. This
15 regulator will be managed during the PHY power on/off sequence.
19 phys: phy {
24 #phy-cells = <1>;
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| D | phy-da8xx-usb.txt | 1 TI DA8xx/OMAP-L1xx/AM18xx USB PHY
4 - compatible: must be "ti,da830-usb-phy".
5 - #phy-cells: must be 1.
7 This device controls the PHY for both the USB 1.1 OHCI and USB 2.0 OTG
8 controllers on DA8xx SoCs. Consumers of this device should use index 0 for
9 the USB 2.0 phy device and index 1 for the USB 1.1 phy device.
11 It also requires a "syscon" node with compatible = "ti,da830-cfgchip", "syscon"
17 compatible = "ti,da830-cfgchip", "syscon";
21 usb_phy: usb-phy {
22 compatible = "ti,da830-usb-phy";
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| D | rcar-gen2-phy.txt | 1 * Renesas R-Car generation 2 USB PHY
3 This file provides information on what the device node for the R-Car generation
4 2 USB PHY contains.
7 - compatible: "renesas,usb-phy-r8a7743" if the device is a part of R8A7743 SoC.
8 "renesas,usb-phy-r8a7744" if the device is a part of R8A7744 SoC.
9 "renesas,usb-phy-r8a7745" if the device is a part of R8A7745 SoC.
10 "renesas,usb-phy-r8a77470" if the device is a part of R8A77470 SoC.
11 "renesas,usb-phy-r8a7790" if the device is a part of R8A7790 SoC.
12 "renesas,usb-phy-r8a7791" if the device is a part of R8A7791 SoC.
13 "renesas,usb-phy-r8a7794" if the device is a part of R8A7794 SoC.
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| D | rcar-gen3-phy-usb3.txt | 1 * Renesas R-Car generation 3 USB 3.0 PHY
3 This file provides information on what the device node for the R-Car generation
4 3 and RZ/G2 USB 3.0 PHY contain.
10 - compatible: "renesas,r8a774a1-usb3-phy" if the device is a part of an R8A774A1
12 "renesas,r8a7795-usb3-phy" if the device is a part of an R8A7795
14 "renesas,r8a7796-usb3-phy" if the device is a part of an R8A7796
16 "renesas,r8a77965-usb3-phy" if the device is a part of an
18 "renesas,rcar-gen3-usb3-phy" for a generic R-Car Gen3 or RZ/G2
19 compatible device.
22 SoC-specific version corresponding to the platform first
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| D | samsung-phy.txt | 2 -------------------------------------------------
5 - compatible : should be one of the listed compatibles:
6 - "samsung,s5pv210-mipi-video-phy"
7 - "samsung,exynos5420-mipi-video-phy"
8 - "samsung,exynos5433-mipi-video-phy"
9 - #phy-cells : from the generic phy bindings, must be 1;
12 - syscon - phandle to the PMU system controller
14 In case of exynos5433 compatible PHY:
15 - samsung,pmu-syscon - phandle to the PMU system controller
16 - samsung,disp-sysreg - phandle to the DISP system registers controller
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| D | phy-mvebu.txt | 1 * Marvell MVEBU SATA PHY
3 Power control for the SATA phy found on Marvell MVEBU SoCs.
5 This document extends the binding described in phy-bindings.txt
9 - reg : Offset and length of the register set for the SATA device
10 - compatible : Should be "marvell,mvebu-sata-phy"
11 - clocks : phandle of clock and specifier that supplies the device
12 - clock-names : Should be "sata"
15 sata-phy@84000 {
16 compatible = "marvell,mvebu-sata-phy";
19 clock-names = "sata";
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| D | phy-hi3798cv200-combphy.txt | 1 HiSilicon STB PCIE/SATA/USB3 PHY
4 - compatible: Should be "hisilicon,hi3798cv200-combphy"
5 - reg: Should be the address space for COMBPHY configuration and state
8 - #phy-cells: Should be 1. The cell number is used to select the phy mode
9 as defined in <dt-bindings/phy/phy.h>.
10 - clocks: The phandle to clock provider and clock specifier pair.
11 - resets: The phandle to reset controller and reset specifier pair.
13 Refer to phy/phy-bindings.txt for the generic PHY binding properties.
16 - hisilicon,fixed-mode: If the phy device doesn't support mode select
19 - hisilicon,mode-select-bits: If the phy device support mode select,
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| D | rcar-gen3-phy-pcie.txt | 1 * Renesas R-Car generation 3 PCIe PHY
3 This file provides information on what the device node for the R-Car
4 generation 3 PCIe PHY contains.
7 - compatible: "renesas,r8a77980-pcie-phy" if the device is a part of the
9 - reg: offset and length of the register block.
10 - clocks: clock phandle and specifier pair.
11 - power-domains: power domain phandle and specifier pair.
12 - resets: reset phandle and specifier pair.
13 - #phy-cells: see phy-bindings.txt in the same directory, must be <0>.
15 Example (R-Car V3H):
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| /Documentation/devicetree/bindings/net/ |
| D | fsl-enetc.txt | 1 * ENETC ethernet device tree bindings
5 below device tree bindings.
9 - reg : Specifies PCIe Device Number and Function
10 Number of the ENETC endpoint device, according
12 - compatible : Should be "fsl,enetc".
14 1. The ENETC external port is connected to a MDIO configurable phy
18 In this case, the ENETC node should include a "mdio" sub-node
19 that in turn should contain the "ethernet-phy" node describing the
20 external phy. Below properties are required, their bindings
22 Documentation/devicetree/bindings/net/phy.txt.
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| D | cpsw.txt | 1 TI SoC Ethernet Switch Controller Device Tree Bindings
2 ------------------------------------------------------
5 - compatible : Should be one of the below:-
7 "ti,am335x-cpsw" for AM335x controllers
8 "ti,am4372-cpsw" for AM437x controllers
9 "ti,dra7-cpsw" for DRA7x controllers
10 - reg : physical base address and size of the cpsw
12 - interrupts : property with a value describing the interrupt
14 - cpdma_channels : Specifies number of channels in CPDMA
15 - ale_entries : Specifies No of entries ALE can hold
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| D | fsl-fec.txt | 4 - compatible : Should be "fsl,<soc>-fec"
5 - reg : Address and length of the register set for the device
6 - interrupts : Should contain fec interrupt
7 - phy-mode : See ethernet.txt file in the same directory
10 - phy-supply : regulator that powers the Ethernet PHY.
11 - phy-handle : phandle to the PHY device connected to this device.
12 - fixed-link : Assume a fixed link. See fixed-link.txt in the same directory.
13 Use instead of phy-handle.
14 - fsl,num-tx-queues : The property is valid for enet-avb IP, which supports
17 - fsl,num-rx-queues : The property is valid for enet-avb IP, which supports
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| D | socionext-netsec.txt | 4 - compatible: Should be "socionext,synquacer-netsec"
5 - reg: Address and length of the control register area, followed by the
8 - interrupts: Should contain ethernet controller interrupt
9 - clocks: phandle to the PHY reference clock
10 - clock-names: Should be "phy_ref_clk"
11 - phy-mode: See ethernet.txt file in the same directory
12 - phy-handle: See ethernet.txt in the same directory.
14 - mdio device tree subnode: When the Netsec has a phy connected to its local
15 mdio, there must be device tree subnode with the following
18 - #address-cells: Must be <1>.
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| D | qcom-emac.txt | 4 internal PHY. Each device is represented by a device tree node. A phandle
5 connects the MAC node to its corresponding internal phy node. Another
6 phandle points to the external PHY node.
11 - compatible : Should be "qcom,fsm9900-emac".
12 - reg : Offset and length of the register regions for the device
13 - interrupts : Interrupt number used by this controller
14 - mac-address : The 6-byte MAC address. If present, it is the default
16 - internal-phy : phandle to the internal PHY node
17 - phy-handle : phandle the the external PHY node
19 Internal PHY node:
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| D | xilinx_axienet.txt | 1 XILINX AXI ETHERNET Device Tree Bindings
2 --------------------------------------------------------
5 provides connectivity to an external ethernet PHY supporting different
15 For more details about mdio please refer phy.txt file in the same directory.
18 - compatible : Must be one of "xlnx,axi-ethernet-1.00.a",
19 "xlnx,axi-ethernet-1.01.a", "xlnx,axi-ethernet-2.01.a"
20 - reg : Address and length of the IO space, as well as the address
22 axistream-connected is specified, in which case the reg
24 - interrupts : Should be a list of 2 or 3 interrupts: TX DMA, RX DMA,
25 and optionally Ethernet core. If axistream-connected is
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| D | apm-xgene-enet.txt | 1 APM X-Gene SoC Ethernet nodes
3 Ethernet nodes are defined to describe on-chip ethernet interfaces in
4 APM X-Gene SoC.
7 - compatible: Should state binding information from the following list,
8 - "apm,xgene-enet": RGMII based 1G interface
9 - "apm,xgene1-sgenet": SGMII based 1G interface
10 - "apm,xgene1-xgenet": XFI based 10G interface
11 - reg: Address and length of the register set for the device. It contains the
12 information of registers in the same order as described by reg-names
13 - reg-names: Should contain the register set names
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| /Documentation/networking/ |
| D | phy.rst | 2 PHY Abstraction Layer
10 PHY. The PHY concerns itself with negotiating link parameters with the link
17 the PHY management code with the network driver. This has resulted in large
23 accessed are, in fact, busses, the PHY Abstraction Layer treats them as such.
26 #. Increase code-reuse
27 #. Increase overall code-maintainability
30 Basically, this layer is meant to provide an interface to PHY devices which
37 Most network devices are connected to a PHY by means of a management bus.
40 registered as a distinct device.
47 mii_id is the address on the bus for the PHY, and regnum is the register
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| /Documentation/devicetree/bindings/usb/ |
| D | msm-hsusb.txt | 6 - compatible: Should contain "qcom,ehci-host"
7 - regs: offset and length of the register set in the memory map
8 - usb-phy: phandle for the PHY device
10 Example EHCI controller device node:
13 compatible = "qcom,ehci-host";
15 usb-phy = <&usb_otg>;
18 USB PHY with optional OTG:
21 - compatible: Should contain:
22 "qcom,usb-otg-ci" for chipsets with ChipIdea 45nm PHY
23 "qcom,usb-otg-snps" for chipsets with Synopsys 28nm PHY
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| D | omap-usb.txt | 4 - compatible : Should be "ti,omap4-musb" or "ti,omap3-musb"
5 - ti,hwmods : must be "usb_otg_hs"
6 - multipoint : Should be "1" indicating the musb controller supports
7 multipoint. This is a MUSB configuration-specific setting.
8 - num-eps : Specifies the number of endpoints. This is also a
9 MUSB configuration-specific setting. Should be set to "16"
10 - ram-bits : Specifies the ram address size. Should be set to "12"
11 - interface-type : This is a board specific setting to describe the type of
12 interface between the controller and the phy. It should be "0" or "1"
14 - mode : Should be "3" to represent OTG. "1" signifies HOST and "2"
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| D | cdns-usb3.txt | 1 Binding for the Cadence USBSS-DRD controller
4 - reg: Physical base address and size of the controller's register areas.
6 - HOST registers area
7 - DEVICE registers area
8 - OTG/DRD registers area
9 - reg-names - register memory area names:
10 "xhci" - for HOST registers space
11 "dev" - for DEVICE registers space
12 "otg" - for OTG/DRD registers space
13 - compatible: Should contain: "cdns,usb3"
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| /Documentation/devicetree/bindings/display/msm/ |
| D | hdmi.txt | 4 - compatible: one of the following
5 * "qcom,hdmi-tx-8996"
6 * "qcom,hdmi-tx-8994"
7 * "qcom,hdmi-tx-8084"
8 * "qcom,hdmi-tx-8974"
9 * "qcom,hdmi-tx-8660"
10 * "qcom,hdmi-tx-8960"
11 - reg: Physical base address and length of the controller's registers
12 - reg-names: "core_physical"
13 - interrupts: The interrupt signal from the hdmi block.
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| D | dsi.txt | 5 - compatible:
6 * "qcom,mdss-dsi-ctrl"
7 - reg: Physical base address and length of the registers of controller
8 - reg-names: The names of register regions. The following regions are required:
10 - interrupts: The interrupt signal from the DSI block.
11 - power-domains: Should be <&mmcc MDSS_GDSC>.
12 - clocks: Phandles to device clocks.
13 - clock-names: the following clocks are required:
25 - assigned-clocks: Parents of "byte" and "pixel" for the given platform.
26 - assigned-clock-parents: The Byte clock and Pixel clock PLL outputs provided
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| /Documentation/ABI/testing/ |
| D | sysfs-class-net-phydev | 1 What: /sys/class/mdio_bus/<bus>/<device>/attached_dev
6 Symbolic link to the network device this PHY device is
9 What: /sys/class/mdio_bus/<bus>/<device>/phy_has_fixups
14 This attribute contains the boolean value whether a given PHY
15 device has had any "fixup" workaround running on it, encoded as
17 PHY configurations.
19 What: /sys/class/mdio_bus/<bus>/<device>/phy_id
24 This attribute contains the 32-bit PHY Identifier as reported
25 by the device during bus enumeration, encoded in hexadecimal.
26 This ID is used to match the device with the appropriate
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