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/Documentation/devicetree/bindings/clock/
Dst,stm32-rcc.txt4 The RCC IP is both a reset and a clock controller.
11 "st,stm32f42xx-rcc"
12 "st,stm32f469-rcc"
13 "st,stm32f746-rcc"
14 "st,stm32f769-rcc"
29 rcc: rcc@40023800 {
32 compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
42 The secondary index is the bit number within the RCC register bank, starting
43 from the first RCC clock enable register (RCC_AHB1ENR, address offset 0x30).
49 drivers of the RCC IP, macros are available to generate the index in
[all …]
Dst,stm32h7-rcc.txt4 The RCC IP is both a reset and a clock controller.
11 "st,stm32h743-rcc"
31 rcc: reset-clock-controller@58024400 {
32 compatible = "st,stm32h743-rcc", "st,stm32-rcc";
50 clocks = <&rcc TIM5_CK>;
59 The index is the bit number within the RCC registers bank, starting from RCC
70 resets = <&rcc STM32H7_APB1L_RESET(TIM2)>;
Dst,stm32mp1-rcc.txt4 The RCC IP is both a reset and a clock controller.
6 RCC makes also power management (resume/supend and wakeup interrupt).
15 - compatible: "st,stm32mp1-rcc", "syscon"
25 rcc: rcc@50000000 {
26 compatible = "st,stm32mp1-rcc", "syscon";
47 The index is the bit number within the RCC registers bank, starting from RCC
/Documentation/devicetree/bindings/rtc/
Dst,stm32-rtc.txt33 clocks = <&rcc 1 CLK_RTC>;
34 assigned-clocks = <&rcc 1 CLK_RTC>;
35 assigned-clock-parents = <&rcc 1 CLK_LSE>;
44 clocks = <&rcc RTCAPB_CK>, <&rcc RTC_CK>;
46 assigned-clocks = <&rcc RTC_CK>;
47 assigned-clock-parents = <&rcc LSE_CK>;
57 clocks = <&rcc RTCAPB>, <&rcc RTC>;
/Documentation/devicetree/bindings/net/
Dstm32-dwmac.txt27 - st,eth-clk-sel (boolean) : set this property in RGMII PHY when you want to select RCC clock inste…
28 …ty in RMII mode when you have PHY without crystal 50MHz and want to select RCC clock instead of ET…
39 clocks = <&rcc 0 25>, <&rcc 0 26>, <&rcc 0 27>;
/Documentation/devicetree/bindings/remoteproc/
Dstm32-rproc.txt16 - st,syscfg-tz: Reference to the system configuration which holds the RCC trust
19 2nd cell: register offset containing the RCC trust zone mode setting
20 3rd cell: register bitmask for the RCC trust zone mode bit
60 resets = <&rcc MCU_R>;
61 st,syscfg-holdboot = <&rcc 0x10C 0x1>;
62 st,syscfg-tz = <&rcc 0x000 0x1>;
/Documentation/devicetree/bindings/display/
Dst,stm32-ltdc.txt11 - resets: reset to be used by the device (defined by use of RCC macro).
63 resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
64 clocks = <&rcc 1 CLK_LCD>;
85 resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
86 clocks = <&rcc 1 CLK_LCD>;
102 clocks = <&rcc 1 CLK_F469_DSI>, <&clk_hse>;
104 resets = <&rcc STM32F4_APB2_RESET(DSI)>;
/Documentation/devicetree/bindings/sound/
Dst,stm32-i2s.txt40 clocks = <&rcc PCLK1>, <&rcc SPI2_CK>, <&rcc PLL1_Q>, <&rcc PLL2_P>;
Dst,stm32-sai.txt78 clocks = <&rcc SAI1_CK>, <&rcc PLL1_Q>, <&rcc PLL2_P>;
85 clocks = <&rcc SAI1_CK>;
/Documentation/devicetree/bindings/reset/
Dst,stm32-rcc.txt4 The RCC IP is both a reset and a clock controller.
6 Please see Documentation/devicetree/bindings/clock/st,stm32-rcc.txt
Dst,stm32mp1-rcc.txt4 The RCC IP is both a reset and a clock controller.
6 Please see Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.txt
/Documentation/devicetree/bindings/i2c/
Di2c-stm32.txt47 resets = <&rcc 277>;
48 clocks = <&rcc 0 149>;
60 resets = <&rcc STM32F7_APB1_RESET(I2C1)>;
61 clocks = <&rcc 1 CLK_I2C1>;
/Documentation/devicetree/bindings/crypto/
Dst,stm32-cryp.txt17 clocks = <&rcc 0 STM32F7_AHB2_CLOCK(CRYP)>;
18 resets = <&rcc STM32F7_AHB2_RESET(CRYP)>;
Dst,stm32-hash.txt25 clocks = <&rcc 0 STM32F7_AHB2_CLOCK(HASH)>;
26 resets = <&rcc STM32F7_AHB2_RESET(HASH)>;
Dst,stm32-crc.txt15 clocks = <&rcc 0 12>;
/Documentation/devicetree/bindings/media/
Dst,stm32-dcmi.txt8 see Documentation/devicetree/bindings/reset/st,stm32-rcc.txt
29 resets = <&rcc STM32F4_AHB2_RESET(DCMI)>;
30 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>;
Dst,stm32-cec.txt17 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>;
/Documentation/devicetree/bindings/spi/
Dspi-stm32-qspi.txt35 resets = <&rcc STM32F4_AHB3_RESET(QSPI)>;
36 clocks = <&rcc 0 STM32F4_AHB3_CLOCK(QSPI)>;
Dspi-stm32.txt47 clocks = <&rcc SPI2_CK>;
48 resets = <&rcc 1166>;
/Documentation/devicetree/bindings/mtd/
Dstm32-fmc2-nand.txt48 clocks = <&rcc FMC_K>;
49 resets = <&rcc FMC_R>;
/Documentation/devicetree/bindings/dma/
Dstm32-dmamux.txt39 resets = <&rcc 150>;
59 resets = <&rcc 150>;
/Documentation/devicetree/bindings/arm/stm32/
Dstm32-syscon.txt14 clocks = <&rcc SYSCFG>;
/Documentation/devicetree/bindings/mfd/
Dstm32-timers.txt21 See ../reset/st,stm32-rcc.txt
39 clocks = <&rcc 0 160>;
/Documentation/devicetree/bindings/pinctrl/
Dst,stm32-pinctrl.yaml201 #include <dt-bindings/mfd/stm32f4-rcc.h>
215 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>;
233 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>;
243 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>;
/Documentation/devicetree/bindings/regulator/
Dst,stm32-vrefbuf.txt16 clocks = <&rcc VREF_CK>;

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