Searched refs:operations (Results 1 – 25 of 32) sorted by relevance
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| /arch/unicore32/mm/ |
| D | Kconfig | 35 Say Y here to disable the data cache line operations.
41 Say Y here to disable the TLB single entry operations.
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| /arch/arm/mach-vexpress/ |
| D | dcscb_setup.S | 30 2: @ Implementation-specific local CPU setup operations should go here,
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| /arch/arm/include/asm/ |
| D | page.h | 104 #error Unknown user operations model
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| /arch/arm/mm/ |
| D | Kconfig | 147 instruction sequences for cache and TLB operations. Curiously,
730 trylock() operations with the assumption that the code will not
739 perform SWP operations to uncached memory to deadlock.
808 To support such cache operations, it is efficient to know the size
927 cache maintenance operations and the dma_{map,unmap}_area()
936 processors, if cache maintenance operations are not broadcast
1005 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1008 Invalidate maintenance operations: by Physical Address
1014 as clean lines are not invalidated as a result of these operations.
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| D | proc-sa1100.S | 42 mcr p15, 0, r0, c9, c0, 5 @ Allow read-buffer operations from userland
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| /arch/csky/ |
| D | Kconfig | 78 For SMP, CPU needs "ldex&stex" instructions for atomic operations.
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| /arch/arm/common/ |
| D | mcpm_head.S | 126 @ Wait for any previously-pending cluster teardown operations to abort
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| /arch/m68k/ifpsp060/src/ |
| D | pfpsp.S | 1279 # bit five of the fp extension word separates the monadic and dyadic operations
2401 # This exception handles 3 types of operations: #
2407 # For immediate data operations, the data is read in w/ a #
2608 # SNAN : all operations
2609 # OPERR : all reg-reg or mem-reg operations that can normally operr
2614 # INEX1 : all packed immediate operations
3327 # this would be the case for opclass two operations with a source infinity or
3350 # byte, word, long, and packed destination format operations can pass
3351 # through here. since packed format operations already were handled by
3790 # this would be the case for opclass two operations with a source zero
[all …]
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| /arch/arm/ |
| D | Kconfig | 865 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
876 erratum. For very specific sequences of memory operations, it is
904 between two write operations may not ensure the correct visibility
933 corrects this value, ensuring cache maintenance operations which use
937 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
942 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1035 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1159 bool "ARM errata: Cache maintenance by set/way operations can execute out of order"
1163 operations that do not specify an address execute, relative to
1355 management operations described in ARM document number ARM DEN
[all …]
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| /arch/sparc/include/asm/ |
| D | vio.h | 132 u64 operations; member
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| /arch/x86/crypto/ |
| D | chacha-avx512vl-x86_64.S | 35 # matrix twice across four AVX registers. It performs matrix operations
201 # operations on four words in two matrices in parallel, sequentially
202 # to the operations on the four words of the other two matrices. The
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| D | chacha-avx2-x86_64.S | 45 # matrix twice across four AVX registers. It performs matrix operations
238 # operations on four words in two matrices in parallel, sequentially
239 # to the operations on the four words of the other two matrices. The
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| /arch/ia64/ |
| D | Kconfig | 457 tristate "Memory special operations driver"
462 operations support (formerly known as fetchop), say Y here,
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| /arch/arm/kernel/ |
| D | head.S | 521 @ Cortex-A9 CPU is present but SMP operations fault.
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| /arch/s390/boot/ |
| D | head.S | 339 .quad .Llinkage_stack # cr15: linkage stack operations
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| /arch/sh/ |
| D | Kconfig | 723 bool "Implement atomic operations by roll-back (gRB) (EXPERIMENTAL)"
727 atomic operations using a software implementation of load-locked/
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| /arch/parisc/kernel/ |
| D | perf_asm.S | 87 ;* for RDR10 which has bits that preclude PDC stack operations
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| /arch/powerpc/platforms/ |
| D | Kconfig | 290 bool "Use the platform RTC operations from user space"
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| /arch/sparc/lib/ |
| D | M7memcpy.S | 450 ! ST_CHUNK batches up initial BIS operations for several cache lines
453 ! BIS operations are executed.
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| /arch/x86/ |
| D | Kconfig.debug | 208 delay for certain operations. Should work on most new machines.
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| D | Kconfig.cpu | 205 operations.
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| /arch/powerpc/ |
| D | Kconfig.debug | 121 bool "Restrict xmon to read-only operations by default"
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| /arch/m68k/ |
| D | Kconfig.cpu | 381 some operations. Say N if not sure.
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| /arch/xtensa/ |
| D | Kconfig | 366 fast_syscall_xtensa is a syscall that can make atomic operations
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| /arch/arm64/ |
| D | Kconfig | 1287 trylock() operations with the assumption that the code will not
1296 perform SWP operations to uncached memory to deadlock.
1429 operations if DC CVAP is not supported (following the behaviour of
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