| /arch/x86/kernel/cpu/mce/ |
| D | p5.c | 29 rdmsr(MSR_IA32_P5_MC_ADDR, loaddr, hi); in pentium_machine_check()
30 rdmsr(MSR_IA32_P5_MC_TYPE, lotype, hi); in pentium_machine_check()
63 rdmsr(MSR_IA32_P5_MC_ADDR, l, h); in intel_p5_mcheck_init()
64 rdmsr(MSR_IA32_P5_MC_TYPE, l, h); in intel_p5_mcheck_init()
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| D | therm_throt.c | 442 rdmsr(MSR_IA32_MISC_ENABLE, l, h); in intel_init_thermal()
468 rdmsr(MSR_THERM2_CTL, l, h); in intel_init_thermal()
479 rdmsr(MSR_IA32_THERM_INTERRUPT, l, h); in intel_init_thermal()
493 rdmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h); in intel_init_thermal()
512 rdmsr(MSR_IA32_MISC_ENABLE, l, h); in intel_init_thermal()
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| D | winchip.c | 38 rdmsr(MSR_IDT_FCR1, lo, hi); in winchip_mcheck_init()
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| /arch/x86/kernel/cpu/mtrr/ |
| D | generic.c | 57 rdmsr(MSR_K8_SYSCFG, lo, hi); in k8_check_syscfg_dram_mod_en()
318 rdmsr(MTRRphysBase_MSR(index), vr->base_lo, vr->base_hi); in get_mtrr_var_range()
319 rdmsr(MTRRphysMask_MSR(index), vr->mask_lo, vr->mask_hi); in get_mtrr_var_range()
343 rdmsr(MSR_MTRRfix64K_00000, p[0], p[1]); in get_fixed_ranges()
346 rdmsr(MSR_MTRRfix16K_80000 + i, p[2 + i * 2], p[3 + i * 2]); in get_fixed_ranges()
348 rdmsr(MSR_MTRRfix4K_C0000 + i, p[6 + i * 2], p[7 + i * 2]); in get_fixed_ranges()
471 rdmsr(MSR_MTRRcap, lo, dummy); in get_mtrr_state()
479 rdmsr(MSR_MTRRdefType, lo, dummy); in get_mtrr_state()
487 rdmsr(MSR_K8_TOP_MEM2, low, high); in get_mtrr_state()
543 rdmsr(msr, lo, hi); in set_fixed_range()
[all …]
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| D | amd.c | 15 rdmsr(MSR_K6_UWCCR, low, high); in amd_get_mtrr()
67 rdmsr(MSR_K6_UWCCR, regs[0], regs[1]); in amd_set_mtrr()
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| /arch/x86/kernel/cpu/ |
| D | centaur.c | 38 rdmsr(MSR_VIA_FCR, lo, hi); in init_c3()
46 rdmsr(MSR_VIA_RNG, lo, hi); in init_c3()
60 rdmsr(MSR_VIA_FCR, lo, hi); in init_c3()
126 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high); in centaur_detect_vmx_virtcap()
134 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2, in centaur_detect_vmx_virtcap()
218 rdmsr(MSR_IDT_FCR1, lo, hi); in init_centaur()
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| D | zhaoxin.c | 36 rdmsr(MSR_ZHAOXIN_FCR57, lo, hi); in init_zhaoxin_cap()
45 rdmsr(MSR_ZHAOXIN_FCR57, lo, hi); in init_zhaoxin_cap()
96 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high); in zhaoxin_detect_vmx_virtcap()
104 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2, in zhaoxin_detect_vmx_virtcap()
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| D | transmeta.c | 86 rdmsr(0x80860004, cap_mask, uk); in init_transmeta()
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| D | intel.c | 609 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high); in detect_vmx_virtcap()
616 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2, in detect_vmx_virtcap()
624 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP, in detect_vmx_virtcap()
701 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2); in init_intel()
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| D | amd.c | 238 rdmsr(MSR_K6_WHCR, l, h); in init_amd_k6()
259 rdmsr(MSR_K6_WHCR, l, h); in init_amd_k6()
306 rdmsr(MSR_K7_CLK_CTL, l, h); in init_amd_k7()
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| /arch/x86/kernel/ |
| D | tsc_msr.c | 180 rdmsr(MSR_PLATFORM_INFO, lo, hi); in cpu_khz_from_msr()
183 rdmsr(MSR_IA32_PERF_STATUS, lo, hi); in cpu_khz_from_msr()
188 rdmsr(MSR_FSB_FREQ, lo, hi); in cpu_khz_from_msr()
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| D | verify_cpu.S | 94 rdmsr
126 rdmsr
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| D | head_64.S | 152 rdmsr
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| /arch/x86/oprofile/ |
| D | op_model_p4.c | 534 rdmsr(ev->bindings[i].escr_address, escr, high); in pmc_setup_one_p4_counter()
548 rdmsr(p4_counters[VIRT_CTR(stag, ctr)].cccr_address, in pmc_setup_one_p4_counter()
578 rdmsr(MSR_IA32_MISC_ENABLE, low, high); in p4_setup_ctrs()
588 rdmsr(p4_counters[VIRT_CTR(stag, i)].cccr_address, low, high); in p4_setup_ctrs()
647 rdmsr(p4_counters[real].cccr_address, low, high); in p4_check_ctrs()
648 rdmsr(p4_counters[real].counter_address, ctr, high); in p4_check_ctrs()
678 rdmsr(p4_counters[VIRT_CTR(stag, i)].cccr_address, low, high); in p4_start()
695 rdmsr(p4_counters[VIRT_CTR(stag, i)].cccr_address, low, high); in p4_stop()
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| /arch/x86/mm/ |
| D | mem_encrypt_boot.S | 114 rdmsr
147 rdmsr
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| /arch/x86/boot/compressed/ |
| D | efi_thunk_64.S | 132 rdmsr
159 rdmsr
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| D | mem_encrypt.S | 49 rdmsr
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| D | head_64.S | 189 rdmsr
633 rdmsr
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| /arch/x86/hyperv/ |
| D | hv_apic.c | 62 rdmsr(HV_X64_MSR_EOI, reg_val, hi); in hv_apic_read()
65 rdmsr(HV_X64_MSR_TPR, reg_val, hi); in hv_apic_read()
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| /arch/x86/lib/ |
| D | msr-reg.S | 91 op_safe_regs rdmsr
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| D | msr-smp.c | 19 rdmsr(rv->msr_no, reg->l, reg->h); in __rdmsr_on_cpu()
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| /arch/x86/platform/pvh/ |
| D | head.S | 81 rdmsr
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| /arch/x86/include/asm/ |
| D | msr.h | 266 #define rdmsr(msr, low, high) \ macro
354 rdmsr(msr_no, *l, *h); in rdmsr_on_cpu()
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| /arch/x86/realmode/rm/ |
| D | trampoline_64.S | 105 rdmsr
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| /arch/x86/entry/ |
| D | calling.h | 330 rdmsr
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