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/arch/arm64/boot/dts/hisilicon/
Dhi3798cv200.dtsi121 resets = <&crg 0xbc 4>;
128 resets = <&crg 0xbc 8>;
134 resets = <&crg 0xbc 9>;
142 resets = <&crg 0xbc 6>;
149 resets = <&crg 0xbc 10>;
Dhikey-pinctrl.dtsi151 0xbc MUX_M1 /* BL_PWM (IOMG047) */
509 0xbc 0x0 /* PWM_IN (IOCFG047) */
Dhikey960-pinctrl.dtsi852 reg = <0x0 0xfff11800 0x0 0xbc>;
/arch/parisc/include/asm/
Dpdcpat.h344 } xbc[8*4]; member
/arch/mips/boot/dts/ingenic/
Djz4740.dtsi260 reg = <0x13020000 0xbc
/arch/arm/boot/dts/
Dam33xx-clocks.dtsi560 reg = <0x24 0xc>, <0x94 0x10>, <0xbc 0x4>, <0xdc 0x8>, <0xfc 0x8>;
Dr8a7794.dtsi1006 dmas = <&audma0 0xbc>;
Dr8a7793.dtsi1039 dmas = <&audma1 0xbc>;
Dr8a7745.dtsi1167 dmas = <&audma0 0xbc>;
Dr8a7790.dtsi1157 dmas = <&audma1 0xbc>;
Dr8a7744.dtsi1233 dmas = <&audma1 0xbc>;
Dr8a7743.dtsi1233 dmas = <&audma1 0xbc>;
Dr8a7791.dtsi1195 dmas = <&audma1 0xbc>;
/arch/arm64/boot/dts/mediatek/
Dmt8173.dtsi475 reg = <0 0x10013000 0 0xbc>;
/arch/arm64/boot/dts/renesas/
Dr8a77990.dtsi1338 dmas = <&audma0 0xbc>;
Dr8a774c0.dtsi1383 dmas = <&audma0 0xbc>;
Dr8a774a1.dtsi1742 dmas = <&audma1 0xbc>;
Dr8a77965.dtsi1593 dmas = <&audma1 0xbc>;
Dr8a7796.dtsi1849 dmas = <&audma1 0xbc>;
Dr8a7795.dtsi1969 dmas = <&audma1 0xbc>;