/arch/powerpc/math-emu/ |
D | math.c | 28 #define FLOATFUNC(x) static inline int x(void *op1, void *op2, void *op3, \ 228 void *op0 = 0, *op1 = 0, *op2 = 0, *op3 = 0; in do_mathemu() local 333 op1 = (void *)¤t->thread.TS_FPR((insn >> 16) & 0x1f); in do_mathemu() 339 op1 = (void *)¤t->thread.TS_FPR((insn >> 16) & 0x1f); in do_mathemu() 345 op1 = (void *)¤t->thread.TS_FPR((insn >> 16) & 0x1f); in do_mathemu() 354 op1 = (void *)((idx ? regs->gpr[idx] : 0) + sdisp); in do_mathemu() 364 op1 = (void *)(regs->gpr[idx] + sdisp); in do_mathemu() 373 op1 = (void *)¤t->thread.TS_FPR((insn >> 16) & 0x1f); in do_mathemu() 378 op1 = (void *)¤t->thread.TS_FPR((insn >> 11) & 0x1f); in do_mathemu() 384 op1 = (void *)((idx ? regs->gpr[idx] : 0) in do_mathemu() [all …]
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/arch/arm/include/asm/ |
D | atomic.h | 306 #define ATOMIC64_OP(op, op1, op2) \ argument 315 " " #op1 " %Q0, %Q0, %Q4\n" \ 325 #define ATOMIC64_OP_RETURN(op, op1, op2) \ argument 336 " " #op1 " %Q0, %Q0, %Q4\n" \ 348 #define ATOMIC64_FETCH_OP(op, op1, op2) \ argument 359 " " #op1 " %Q1, %Q0, %Q5\n" \ 371 #define ATOMIC64_OPS(op, op1, op2) \ argument 372 ATOMIC64_OP(op, op1, op2) \ 373 ATOMIC64_OP_RETURN(op, op1, op2) \ 374 ATOMIC64_FETCH_OP(op, op1, op2) [all …]
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/arch/sh/kernel/ |
D | kprobes.c | 149 struct kprobe *op1, *op2; in prepare_singlestep() local 153 op1 = this_cpu_ptr(&saved_next_opcode); in prepare_singlestep() 158 op1->addr = (kprobe_opcode_t *) regs->regs[reg_nr]; in prepare_singlestep() 161 op1->addr = in prepare_singlestep() 166 op1->addr = in prepare_singlestep() 171 op1->addr = (kprobe_opcode_t *) regs->pr; in prepare_singlestep() 176 op1->addr = p->addr + 1; in prepare_singlestep() 186 op1->addr = p->addr + 2; in prepare_singlestep() 194 op1->addr = p->addr + 1; in prepare_singlestep() 197 op1->opcode = *(op1->addr); in prepare_singlestep() [all …]
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/arch/arc/include/asm/ |
D | atomic.h | 361 #define ATOMIC64_OP(op, op1, op2) \ 369 " " #op1 " %L0, %L0, %L2 \n" \ 378 #define ATOMIC64_OP_RETURN(op, op1, op2) \ 388 " " #op1 " %L0, %L0, %L2 \n" \ 401 #define ATOMIC64_FETCH_OP(op, op1, op2) \ 411 " " #op1 " %L1, %L0, %L3 \n" \ 424 #define ATOMIC64_OPS(op, op1, op2) \ 425 ATOMIC64_OP(op, op1, op2) \ 426 ATOMIC64_OP_RETURN(op, op1, op2) \ 427 ATOMIC64_FETCH_OP(op, op1, op2)
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/arch/arm64/include/asm/ |
D | esr.h | 175 #define ESR_ELx_SYS64_ISS_SYS_VAL(op0, op1, op2, crn, crm) \ argument 177 ((op1) << ESR_ELx_SYS64_ISS_OP1_SHIFT) | \ 284 #define ESR_ELx_CP15_32_ISS_SYS_VAL(op1, op2, crn, crm) \ argument 285 (((op1) << ESR_ELx_CP15_32_ISS_OP1_SHIFT) | \ 305 #define ESR_ELx_CP15_64_ISS_SYS_VAL(op1, crm) \ argument 306 (((op1) << ESR_ELx_CP15_64_ISS_OP1_SHIFT) | \
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D | sysreg.h | 36 #define sys_reg(op0, op1, crn, crm, op2) \ argument 37 (((op0) << Op0_shift) | ((op1) << Op1_shift) | \ 88 #define pstate_field(op1, op2) ((op1) << Op1_shift | (op2) << Op2_shift) argument
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/arch/arm/include/uapi/asm/ |
D | kvm.h | 165 #define __ARM_CP15_REG(op1,crn,crm,op2) \ argument 167 ARM_CP15_REG_SHIFT_MASK(op1, OPC1) | \ 174 #define __ARM_CP15_REG64(op1,crm) \ argument 175 (__ARM_CP15_REG(op1, 0, crm, 0) | KVM_REG_SIZE_U64)
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/arch/x86/crypto/ |
D | cast6-avx-x86_64-asm_64.S | 85 #define lookup_32bit(src, dst, op1, op2, op3, interleave_op, il_reg) \ argument 90 op1 s2(, RID2, 4), dst ## d; \ 111 #define F_tail(a, x, gi1, gi2, op1, op2, op3) \ argument 112 lookup_32bit(##gi1, RFS1, op1, op2, op3, shr_next, ##gi1); \ 113 lookup_32bit(##gi2, RFS3, op1, op2, op3, shr_next, ##gi2); \ 115 lookup_32bit(##gi1, RFS2, op1, op2, op3, dummy, none); \ 118 lookup_32bit(##gi2, RFS1, op1, op2, op3, dummy, none); \ 125 #define F_2(a1, b1, a2, b2, op0, op1, op2, op3) \ argument 129 F_tail(b1, RX, RGI1, RGI2, op1, op2, op3); \ 130 F_tail(b2, RTMP, RGI3, RGI4, op1, op2, op3); \
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D | cast5-avx-x86_64-asm_64.S | 85 #define lookup_32bit(src, dst, op1, op2, op3, interleave_op, il_reg) \ argument 90 op1 s2(, RID2, 4), dst ## d; \ 111 #define F_tail(a, x, gi1, gi2, op1, op2, op3) \ argument 112 lookup_32bit(##gi1, RFS1, op1, op2, op3, shr_next, ##gi1); \ 113 lookup_32bit(##gi2, RFS3, op1, op2, op3, shr_next, ##gi2); \ 115 lookup_32bit(##gi1, RFS2, op1, op2, op3, dummy, none); \ 118 lookup_32bit(##gi2, RFS1, op1, op2, op3, dummy, none); \ 125 #define F_2(a1, b1, a2, b2, op0, op1, op2, op3) \ argument 129 F_tail(b1, RX, RGI1, RGI2, op1, op2, op3); \ 130 F_tail(b2, RTMP, RGI3, RGI4, op1, op2, op3); \
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D | twofish-x86_64-asm_64-3way.S | 77 #define do16bit_ror(rot, op1, op2, T0, T1, tmp1, tmp2, ab, dst) \ argument 81 op1##l T0(CTX, tmp2, 4), dst ## d; \
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/arch/x86/kvm/vmx/ |
D | ops.h | 140 #define vmx_asm1(insn, op1, error_args...) \ argument 146 : : op1 : "cc" : error, fault); \ 155 #define vmx_asm2(insn, op1, op2, error_args...) \ argument 161 : : op1, op2 : "cc" : error, fault); \
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/arch/s390/net/ |
D | bpf_jit_comp.c | 195 #define _EMIT6(op1, op2) \ argument 198 *(u32 *) (jit->prg_buf + jit->prg) = op1; \ 204 #define _EMIT6_DISP(op1, op2, disp) \ argument 207 _EMIT6(op1 | __disp, op2); \ 210 #define _EMIT6_DISP_LH(op1, op2, disp) \ argument 215 _EMIT6(op1 | __disp_l, op2 | __disp_h >> 4); \ 218 #define EMIT6_DISP_LH(op1, op2, b1, b2, b3, disp) \ argument 220 _EMIT6_DISP_LH(op1 | reg(b1, b2) << 16 | \ 227 #define EMIT6_PCREL_LABEL(op1, op2, b1, b2, label, mask) \ argument 230 _EMIT6(op1 | reg(b1, b2) << 16 | (rel & 0xffff), \ [all …]
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/arch/arm64/include/uapi/asm/ |
D | kvm.h | 207 #define __ARM64_SYS_REG(op0,op1,crn,crm,op2) \ argument 210 ARM64_SYS_REG_SHIFT_MASK(op1, OP1) | \
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/arch/s390/include/asm/ |
D | percpu.h | 66 #define arch_this_cpu_add(pcp, val, op1, op2, szcast) \ argument 82 op1 " %[old__],%[val__],%[ptr__]\n" \
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/arch/powerpc/include/asm/ |
D | mpc52xx_psc.h | 203 u8 op1; /* PSC + 0x38 */ member 344 u8 op1; /* PSC + 0x48 */ member
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/arch/powerpc/kernel/trace/ |
D | ftrace.c | 482 expected_nop_sequence(void *ip, unsigned int op0, unsigned int op1) in expected_nop_sequence() argument 493 if ((op0 != 0x48000008) || ((op1 & 0xffff0000) != 0xe8410000)) in expected_nop_sequence() 499 expected_nop_sequence(void *ip, unsigned int op0, unsigned int op1) in expected_nop_sequence() argument
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/arch/arm/include/asm/hardware/ |
D | cp14.h | 17 #define MRC14(op1, crn, crm, op2) \ argument 20 asm volatile("mrc p14, "#op1", %0, "#crn", "#crm", "#op2 : "=r" (val)); \ 24 #define MCR14(val, op1, crn, crm, op2) \ argument 26 asm volatile("mcr p14, "#op1", %0, "#crn", "#crm", "#op2 : : "r" (val));\
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/arch/arm/kvm/ |
D | coproc.c | 800 #define FUNCTION_FOR32(crn, crm, op1, op2, name) \ argument 806 asm volatile("mrc p15, " __stringify(op1) \
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/arch/arm64/boot/dts/rockchip/ |
D | rk3399-gru.dtsi | 10 #include "rk3399-op1-opp.dtsi"
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/arch/m68k/ifpsp060/src/ |
D | fpsp.S | 15847 # FP_SRC(a6) = fp op1(src) # 15851 # FP_SRC(a6) = fp op1 scaled(src) #
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