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/Documentation/devicetree/bindings/powerpc/fsl/
Dl2cache.txt1 Freescale L2 Cache Controller
9 "fsl,8540-l2-cache-controller"
10 "fsl,8541-l2-cache-controller"
11 "fsl,8544-l2-cache-controller"
12 "fsl,8548-l2-cache-controller"
13 "fsl,8555-l2-cache-controller"
14 "fsl,8568-l2-cache-controller"
15 "fsl,b4420-l2-cache-controller"
16 "fsl,b4860-l2-cache-controller"
17 "fsl,bsc9131-l2-cache-controller"
[all …]
/Documentation/devicetree/bindings/interrupt-controller/
Dfsl,ls-scfg-msi.txt1 * Freescale Layerscape SCFG PCIe MSI controller
6 Layerscape PCIe MSI controller block such as:
12 - msi-controller: indicates that this is a PCIe MSI controller node
13 - reg: physical base address of the controller and length of memory mapped.
14 - interrupts: an interrupt to the parent interrupt controller.
16 This interrupt controller hardware is a second level interrupt controller that
17 is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
19 controller will be used.
21 MSI controller node
25 msi1: msi-controller@1571000 {
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Dsnps,dw-apb-ictl.txt1 Synopsys DesignWare APB interrupt controller (dw_apb_ictl)
3 Synopsys DesignWare provides interrupt controller IP for APB known as
4 dw_apb_ictl. The IP is used as secondary interrupt controller in some SoCs with
6 controller in some SoCs, e.g. Hisilicon SD5203.
10 - reg: physical base address of the controller and length of memory mapped
12 - interrupt-controller: identifies the node as an interrupt controller
15 Additional required property when it's used as secondary interrupt controller:
16 - interrupts: interrupt reference to primary interrupt controller
27 /* dw_apb_ictl is used as secondary interrupt controller */
28 aic: interrupt-controller@3000 {
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Dfaraday,ftintc010.txt1 * Faraday Technologt FTINTC010 interrupt controller
3 This interrupt controller is a stock IP block from Faraday Technology found
9 "cortina,gemini-interrupt-controller" (deprecated)
10 - reg: The register bank for the interrupt controller.
11 - interrupt-controller: Identifies the node as an interrupt controller
13 Must be 2 as the controller can specify level or rising edge
16 interrupt-controller/interrupts.txt
20 interrupt-controller@48000000 {
23 interrupt-controller;
Dandestech,ativic32.txt1 * Andestech Internal Vector Interrupt Controller
3 The Internal Vector Interrupt Controller (IVIC) is a basic interrupt controller
5 bigger External Vector Interrupt Controller.
11 - interrupt-controller : Identifies the node as an interrupt controller
12 - #interrupt-cells: 1 cells and refer to interrupt-controller/interrupts
15 intc: interrupt-controller {
18 interrupt-controller;
Dsigma,smp8642-intc.txt1 Sigma Designs SMP86xx/SMP87xx secondary interrupt controller
7 - interrupt-controller: boolean
13 - interrupt-controller: boolean
15 - interrupts: interrupt spec of primary interrupt controller
19 interrupt-controller@6e000 {
24 interrupt-controller;
28 irq0: interrupt-controller@0 {
30 interrupt-controller;
35 irq1: interrupt-controller@100 {
37 interrupt-controller;
[all …]
Dmarvell,odmi-controller.txt4 Some Marvell SoCs have an On-Die Message Interrupt (ODMI) controller
11 "marvell,ap806-odmi-controller", "marvell,odmi-controller".
13 - interrupt,controller : Identifies the node as an interrupt controller.
15 - msi-controller : Identifies the node as an MSI controller.
26 See Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml
32 compatible = "marvell,ap806-odmi-controller",
33 "marvell,odmi-controller";
34 interrupt-controller;
35 msi-controller;
/Documentation/devicetree/bindings/pinctrl/
Dsamsung-pinctrl.txt1 Samsung GPIO and Pin Mux/Config controller
4 controller. It controls the input/output settings on the available pads/pins
10 - "samsung,s3c2412-pinctrl": for S3C2412-compatible pin-controller,
11 - "samsung,s3c2416-pinctrl": for S3C2416-compatible pin-controller,
12 - "samsung,s3c2440-pinctrl": for S3C2440-compatible pin-controller,
13 - "samsung,s3c2450-pinctrl": for S3C2450-compatible pin-controller,
14 - "samsung,s3c64xx-pinctrl": for S3C64xx-compatible pin-controller,
15 - "samsung,s5pv210-pinctrl": for S5PV210-compatible pin-controller,
16 - "samsung,exynos3250-pinctrl": for Exynos3250 compatible pin-controller.
17 - "samsung,exynos4210-pinctrl": for Exynos4210 compatible pin-controller.
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/Documentation/devicetree/bindings/clock/
Dexynos5433-clock.txt3 The Exynos5433 clock controller generates and supplies clock to various
9 - "samsung,exynos5433-cmu-top" - clock controller compatible for CMU_TOP
12 - "samsung,exynos5433-cmu-cpif" - clock controller compatible for CMU_CPIF
14 - "samsung,exynos5433-cmu-mif" - clock controller compatible for CMU_MIF
15 which generates clocks for DRAM Memory Controller domain.
16 - "samsung,exynos5433-cmu-peric" - clock controller compatible for CMU_PERIC
18 - "samsung,exynos5433-cmu-peris" - clock controller compatible for CMU_PERIS
20 - "samsung,exynos5433-cmu-fsys" - clock controller compatible for CMU_FSYS
22 - "samsung,exynos5433-cmu-g2d" - clock controller compatible for CMU_G2D
24 - "samsung,exynos5433-cmu-disp" - clock controller compatible for CMU_DISP
[all …]
Dexynos7-clock.txt1 * Samsung Exynos7 Clock Controller
3 Exynos7 clock controller has various blocks which are instantiated
22 Required Properties for Clock Controller:
25 compatible strings to indicate the clock controller
40 - reg: physical base address of the controller and the length of
46 the given clock controller. Please refer the next section to
47 find the input clocks for a given controller.
50 to the given clock controller.
52 Input clocks for top0 clock controller:
60 Input clocks for top1 clock controller:
[all …]
Dexynos5260-clock.txt1 * Samsung Exynos5260 Clock Controller
29 These clocks are fed into the clock controller and then routed to
49 Required Properties for Clock Controller:
66 - reg: physical base address of the controller and the length of
72 the given clock controller. Please refer the next section to find
73 the input clocks for a given controller.
76 to the given clock controller.
78 Input clocks for top clock controller:
84 Input clocks for peri clock controller:
100 Input clocks for egl clock controller:
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Dexynos4-clock.txt1 * Samsung Exynos4 Clock Controller
3 The Exynos4 clock controller generates and supplies clock to various controllers
10 - "samsung,exynos4210-clock" - controller compatible with Exynos4210 SoC.
11 - "samsung,exynos4412-clock" - controller compatible with Exynos4412 SoC.
13 - reg: physical base address of the controller and length of memory mapped
25 Example 1: An example of a clock controller node is listed below.
27 clock: clock-controller@10030000 {
33 Example 2: UART controller node that consumes the clock generated by the clock
34 controller. Refer to the standard clock bindings for information
48 the main clock controller, a separate clock controller has to be defined for
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/Documentation/devicetree/bindings/gpio/
D8xxx_gpio.txt6 Every GPIO controller node must have #gpio-cells property defined,
12 controller, see bindings/interrupt-controller/interrupts.txt (the
16 The GPIO module may serve as another interrupt controller (cascaded to
17 the SoC's internal interrupt controller). See the interrupt controller
18 nodes section in bindings/interrupt-controller/interrupts.txt for
29 - gpio-controller: Marks the port as GPIO controller.
32 - interrupt-controller: Empty boolean property which marks the GPIO
33 module as an IRQ controller.
36 this interrupt controller. The first cell
43 Example of gpio-controller nodes for a MPC8347 SoC:
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Dgpio-mxs.yaml7 title: Freescale MXS GPIO controller
14 The Freescale MXS GPIO controller is part of MXS PIN controller.
16 As the GPIO controller is embedded in the PIN controller and all the
17 GPIO ports share the same IO space with PIN controller, the GPIO node
50 interrupt-controller: true
58 gpio-controller: true
64 - interrupt-controller
67 - gpio-controller
91 gpio-controller;
93 interrupt-controller;
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Dintel,ixp4xx-gpio.txt3 This GPIO controller is found in the Intel IXP4xx processors.
6 The interrupt portions of the GPIO controller is hierarchical:
9 main IXP4xx interrupt controller which has a 1:1 mapping for
15 The interrupt parent of this GPIO controller must be the
16 IXP4xx interrupt controller.
23 - gpio-controller : marks this as a GPIO controller
25 - interrupt-controller : marks this as an interrupt controller
27 interrupt-controller/interrupts.txt
34 gpio-controller;
36 interrupt-controller;
Dgpio-thunderx.txt1 Cavium ThunderX/OCTEON-TX GPIO controller bindings
4 - reg: The controller bus address.
5 - gpio-controller: Marks the device node as a GPIO controller.
7 - First cell is the GPIO pin number relative to the controller.
12 - interrupt-controller: Marks the device node as an interrupt controller.
14 "interrupt-controller" is present.
15 - First cell is the GPIO pin number relative to the controller.
23 gpio-controller;
25 interrupt-controller;
Dbrcm,brcmstb-gpio.txt1 Broadcom STB "UPG GIO" GPIO controller
3 The controller's registers are organized as sets of eight 32-bit
5 interrupt is shared for all of the banks handled by the controller.
14 the brcmstb GPIO controller registers
17 Should be <2>. The first cell is the pin number (within the controller's
21 - gpio-controller:
22 Specifies that the node is a GPIO controller.
31 The interrupt shared by all GPIO lines for this controller.
37 wakeup interrupt lines through a different interrupt controller than the
49 See also Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
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Dgpio-nmk.txt1 Nomadik GPIO controller
5 - reg : Physical base address and length of the controller's registers.
6 - interrupts : The interrupt outputs from the controller.
15 - gpio-controller : Marks the device node as a GPIO controller.
16 - interrupt-controller : Marks the device node as an interrupt controller.
17 - gpio-bank : Specifies which bank a controller owns.
18 - st,supports-sleepmode : Specifies whether controller can sleep or not
27 gpio-controller;
28 interrupt-controller;
/Documentation/devicetree/bindings/pci/
Dpci-msi.txt23 Documentation/devicetree/bindings/interrupt-controller/msi.txt.
32 - msi-map: Maps a Requester ID to an MSI controller and associated
34 (rid-base,msi-controller,msi-base,length), where:
38 * msi-controller is a single phandle to an MSI controller
47 the listed msi-controller, with the msi-specifier (r - rid-base + msi-base).
53 the root complex and MSI controller do not pass sideband data with MSI
54 writes, this property may be used to describe the MSI controller(s)
66 msi: msi-controller@a {
68 compatible = "vendor,some-controller";
69 msi-controller;
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/Documentation/devicetree/bindings/mux/
Dmux-controller.txt1 Common multiplexer controller bindings
4 A multiplexer (or mux) controller will have one, or several, consumer devices
5 that uses the mux controller. Thus, a mux controller can possibly control
7 multiplexer needed by each consumer, but a single mux controller can of course
10 A mux controller provides a number of states to its consumers, and the state
18 Mux controller consumers should specify a list of mux controllers that they
23 mux-ctrl-phandle : phandle to mux controller node
25 given mux controller (controller specific)
27 Mux controller properties should be named "mux-controls". The exact meaning of
28 each mux controller property must be documented in the device tree binding for
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/Documentation/devicetree/bindings/net/can/
Drcar_can.txt1 Renesas R-Car CAN controller Device Tree Bindings
5 - compatible: "renesas,can-r8a7742" if CAN controller is a part of R8A7742 SoC.
6 "renesas,can-r8a7743" if CAN controller is a part of R8A7743 SoC.
7 "renesas,can-r8a7744" if CAN controller is a part of R8A7744 SoC.
8 "renesas,can-r8a7745" if CAN controller is a part of R8A7745 SoC.
9 "renesas,can-r8a77470" if CAN controller is a part of R8A77470 SoC.
10 "renesas,can-r8a774a1" if CAN controller is a part of R8A774A1 SoC.
11 "renesas,can-r8a774b1" if CAN controller is a part of R8A774B1 SoC.
12 "renesas,can-r8a774c0" if CAN controller is a part of R8A774C0 SoC.
13 "renesas,can-r8a774e1" if CAN controller is a part of R8A774E1 SoC.
[all …]
/Documentation/devicetree/bindings/arm/hisilicon/controller/
Dsysctrl.yaml4 $id: http://devicetree.org/schemas/arm/hisilicon/controller/sysctrl.yaml#
7 title: Hisilicon system controller
13 The Hisilicon system controller is used on many Hisilicon boards, it can be
16 There are some variants of the Hisilicon system controller, such as HiP01,
17 Hi3519, Hi6220 system controller, each of them is mostly compatible with the
18 Hisilicon system controller, but some same registers located at different
19 offset. In addition, the HiP01 system controller has some specific control
22 The compatible names of each system controller are as follows:
23 Hisilicon system controller --> hisilicon,sysctrl
24 HiP01 system controller --> hisilicon,hip01-sysctrl
[all …]
/Documentation/devicetree/bindings/memory-controllers/fsl/
Dddr.txt1 Freescale DDR memory controller
5 - compatible : Should include "fsl,chip-memory-controller" where
7 "fsl,qoriq-memory-controller".
8 - reg : Address and size of DDR controller registers
9 - interrupts : Error interrupt of DDR controller
15 memory-controller@2000 {
16 compatible = "fsl,bsc9132-memory-controller";
24 ddr1: memory-controller@8000 {
25 compatible = "fsl,qoriq-memory-controller-v4.7",
26 "fsl,qoriq-memory-controller";
/Documentation/devicetree/bindings/memory-controllers/
Dath79-ddr-controller.txt1 Binding for Qualcomm Atheros AR7xxx/AR9xxx DDR controller
3 The DDR controller of the AR7xxx and AR9xxx families provides an interface
5 by the IRQ controller to flush the FIFO before running the interrupt handler
10 - compatible: has to be "qca,<soc-type>-ddr-controller",
11 "qca,[ar7100|ar7240]-ddr-controller" as fallback.
12 On SoC with PCI support "qca,ar7100-ddr-controller" should be used as
13 fallback, otherwise "qca,ar7240-ddr-controller" should be used.
14 - reg: Base address and size of the controller's memory area
20 ddr_ctrl: memory-controller@18000000 {
21 compatible = "qca,ar9132-ddr-controller",
[all …]
/Documentation/devicetree/bindings/i2c/
Dnvidia,tegra20-i2c.txt1 NVIDIA Tegra20/Tegra30/Tegra114 I2C controller driver.
10 nvidia,tegra20-i2c-dvc: Tegra20 has specific I2C controller called as DVC I2C
11 controller. This only support master mode of I2C communication. Register
13 controller. Driver of DVC I2C controller is only compatible with
15 nvidia,tegra20-i2c: Tegra20 has 4 generic I2C controller. This can support
17 support master mode of I2C communication. Driver of I2C controller is
19 nvidia,tegra30-i2c: Tegra30 has 5 generic I2C controller. This controller is
20 very much similar to Tegra20 I2C controller with additional feature:
22 as per I2C core API transfer flags. Driver of I2C controller is
26 nvidia,tegra114-i2c: Tegra114 has 5 generic I2C controller. This controller is
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