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/Documentation/devicetree/bindings/serial/
Dsnps-dw-apb-uart.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/serial/snps-dw-apb-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare ABP UART
10 - Rob Herring <robh@kernel.org>
13 - $ref: /schemas/serial.yaml#
18 - items:
19 - enum:
20 - renesas,r9a06g032-uart
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/Documentation/devicetree/bindings/clock/
Dbrcm,kona-ccu.txt9 Documentation/devicetree/bindings/clock/clock-bindings.txt
12 - compatible
13 Shall have a value of the form "brcm,<model>-<which>-ccu",
16 "brcm,bcm11351-root-ccu"
19 - reg
22 - #clock-cells
23 Shall have value <1>. The permitted clock-specifier values
25 - clock-output-names
32 compatible = "brcm,bcm11351-slave-ccu";
34 #clock-cells = <1>;
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Drockchip,rv1108-cru.txt9 - compatible: should be "rockchip,rv1108-cru"
10 - reg: physical base address of the controller and length of memory mapped
12 - #clock-cells: should be 1.
13 - #reset-cells: should be 1.
17 - rockchip,grf: phandle to the syscon managing the "general register files"
22 preprocessor macros in the dt-bindings/clock/rv1108-cru.h headers and can be
30 clock-output-names:
31 - "xin24m" - crystal input - required,
32 - "ext_vip" - external VIP clock - optional
33 - "ext_i2s" - external I2S clock - optional
[all …]
Drockchip,rk3036-cru.txt9 - compatible: should be "rockchip,rk3036-cru"
10 - reg: physical base address of the controller and length of memory mapped
12 - #clock-cells: should be 1.
13 - #reset-cells: should be 1.
17 - rockchip,grf: phandle to the syscon managing the "general register files"
22 preprocessor macros in the dt-bindings/clock/rk3036-cru.h headers and can be
30 clock-output-names:
31 - "xin24m" - crystal input - required,
32 - "ext_i2s" - external I2S clock - optional,
33 - "rmii_clkin" - external EMAC clock - optional
[all …]
Drockchip,rk3308-cru.txt9 - compatible: CRU should be "rockchip,rk3308-cru"
10 - reg: physical base address of the controller and length of memory mapped
12 - #clock-cells: should be 1.
13 - #reset-cells: should be 1.
17 - rockchip,grf: phandle to the syscon managing the "general register files"
22 preprocessor macros in the dt-bindings/clock/rk3308-cru.h headers and can be
30 clock-output-names:
31 - "xin24m" - crystal input - required,
32 - "xin32k" - rtc clock - optional,
33 - "mclk_i2s0_8ch_in", "mclk_i2s1_8ch_in", "mclk_i2s2_8ch_in",
[all …]
Dbitmain,bm1880-clk.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/bitmain,bm1880-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
17 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
21 const: bitmain,bm1880-clk
25 - description: pll registers
26 - description: system registers
28 reg-names:
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Drockchip,rk3328-cru.txt9 - compatible: should be "rockchip,rk3328-cru"
10 - reg: physical base address of the controller and length of memory mapped
12 - #clock-cells: should be 1.
13 - #reset-cells: should be 1.
17 - rockchip,grf: phandle to the syscon managing the "general register files"
22 preprocessor macros in the dt-bindings/clock/rk3328-cru.h headers and can be
30 clock-output-names:
31 - "xin24m" - crystal input - required,
32 - "clkin_i2s" - external I2S clock - optional,
33 - "gmac_clkin" - external GMAC clock - optional
[all …]
Drockchip,rk3228-cru.txt9 - compatible: should be "rockchip,rk3228-cru"
10 - reg: physical base address of the controller and length of memory mapped
12 - #clock-cells: should be 1.
13 - #reset-cells: should be 1.
17 - rockchip,grf: phandle to the syscon managing the "general register files"
22 preprocessor macros in the dt-bindings/clock/rk3228-cru.h headers and can be
30 clock-output-names:
31 - "xin24m" - crystal input - required,
32 - "ext_i2s" - external I2S clock - optional,
33 - "ext_gmac" - external GMAC clock - optional
[all …]
Drockchip,rk3399-cru.txt9 - compatible: PMU for CRU should be "rockchip,rk3399-pmucru"
10 - compatible: CRU should be "rockchip,rk3399-cru"
11 - reg: physical base address of the controller and length of memory mapped
13 - #clock-cells: should be 1.
14 - #reset-cells: should be 1.
18 - rockchip,grf: phandle to the syscon managing the "general register files".
24 preprocessor macros in the dt-bindings/clock/rk3399-cru.h headers and can be
32 clock-output-names:
33 - "xin24m" - crystal input - required,
34 - "xin32k" - rtc clock - optional,
[all …]
Drockchip,rk3368-cru.txt9 - compatible: should be "rockchip,rk3368-cru"
10 - reg: physical base address of the controller and length of memory mapped
12 - #clock-cells: should be 1.
13 - #reset-cells: should be 1.
17 - rockchip,grf: phandle to the syscon managing the "general register files"
22 preprocessor macros in the dt-bindings/clock/rk3368-cru.h headers and can be
30 clock-output-names:
31 - "xin24m" - crystal input - required,
32 - "xin32k" - rtc clock - optional,
33 - "ext_i2s" - external I2S clock - optional,
[all …]
Drockchip,rk3188-cru.txt9 - compatible: should be "rockchip,rk3188-cru", "rockchip,rk3188a-cru" or
10 "rockchip,rk3066a-cru"
11 - reg: physical base address of the controller and length of memory mapped
13 - #clock-cells: should be 1.
14 - #reset-cells: should be 1.
18 - rockchip,grf: phandle to the syscon managing the "general register files"
23 preprocessor macros in the dt-bindings/clock/rk3188-cru.h and
24 dt-bindings/clock/rk3066-cru.h headers and can be used in device tree sources.
31 clock-output-names:
32 - "xin24m" - crystal input - required,
[all …]
Drockchip,px30-cru.txt9 - compatible: PMU for CRU should be "rockchip,px30-pmu-cru"
10 - compatible: CRU should be "rockchip,px30-cru"
11 - reg: physical base address of the controller and length of memory mapped
13 - clocks: A list of phandle + clock-specifier pairs for the clocks listed
14 in clock-names
15 - clock-names: Should contain the following:
16 - "xin24m" for both PMUCRU and CRU
17 - "gpll" for CRU (sourced from PMUCRU)
18 - #clock-cells: should be 1.
19 - #reset-cells: should be 1.
[all …]
Drenesas,r9a06g032-sysctrl.txt5 - compatible: Must be:
6 - "renesas,r9a06g032-sysctrl"
7 - reg: Base address and length of the SYSCTRL IO block.
8 - #clock-cells: Must be 1
9 - clocks: References to the parent clocks:
10 - external 40mhz crystal.
11 - external (optional) 32.768khz
12 - external (optional) jtag input
13 - external (optional) RGMII_REFCLK
14 - clock-names: Must be:
[all …]
Drockchip,rk3288-cru.txt8 different so another dt-compatible is available. Noticed that it is only
14 - compatible: should be "rockchip,rk3288-cru" or "rockchip,rk3288w-cru" in
16 - reg: physical base address of the controller and length of memory mapped
18 - #clock-cells: should be 1.
19 - #reset-cells: should be 1.
23 - rockchip,grf: phandle to the syscon managing the "general register files"
28 preprocessor macros in the dt-bindings/clock/rk3288-cru.h headers and can be
36 clock-output-names:
37 - "xin24m" - crystal input - required,
38 - "xin32k" - rtc clock - optional,
[all …]
/Documentation/devicetree/bindings/pinctrl/
Dabilis,tb10x-iomux.txt5 -------------------
7 - compatible: should be "abilis,tb10x-iomux";
8 - reg: should contain the physical address and size of the pin controller's
13 --------------------
15 Functions are defined (and referenced) by sub-nodes of the pin controller.
16 Every sub-node defines exactly one function (implying a set of pins).
19 controller sub-nodes.
22 - abilis,function: should be set to the name of the function's pin group.
25 - GPIO ports: gpioa, gpiob, gpioc, gpiod, gpioe, gpiof, gpiog,
27 - Serial TS input ports: mis0, mis1, mis2, mis3, mis4, mis5, mis6, mis7
[all …]
Drockchip,pinctrl.txt8 Please refer to pinctrl-bindings.txt in this directory for details of the
16 settings such as pull-up, etc.
19 defined as gpio sub-nodes of the pinmux controller.
22 - compatible: should be
23 "rockchip,px30-pinctrl": for Rockchip PX30
24 "rockchip,rv1108-pinctrl": for Rockchip RV1108
25 "rockchip,rk2928-pinctrl": for Rockchip RK2928
26 "rockchip,rk3066a-pinctrl": for Rockchip RK3066a
27 "rockchip,rk3066b-pinctrl": for Rockchip RK3066b
28 "rockchip,rk3128-pinctrl": for Rockchip RK3128
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