Searched +full:on +full:- +full:chip (Results 1 – 25 of 639) sorted by relevance
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/Documentation/userspace-api/media/v4l/ |
D | vidioc-dbg-g-chip-info.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later 13 VIDIOC_DBG_G_CHIP_INFO - Identify the chips on a TV card 40 query the driver about the chips present on the TV card. Regular 41 applications must not use it. When you found a chip specific bug, please 42 contact the linux-media mailing list 52 :ref:`VIDIOC_DBG_G_CHIP_INFO` with a pointer to this structure. On success 53 the driver stores information about the selected chip in the ``name`` 57 selects the nth bridge 'chip' on the TV card. You can enumerate all 60 zero always selects the bridge chip itself, e. g. the chip connected to 61 the PCI or USB bus. Non-zero numbers identify specific parts of the [all …]
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D | vidioc-dbg-g-register.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later 13 VIDIOC_DBG_G_REGISTER - VIDIOC_DBG_S_REGISTER - Read or write hardware registers 55 ``match.type`` and ``match.addr`` or ``match.name`` fields select a chip 56 on the TV card, the ``reg`` field specifies a register number and the 61 ``VIDIOC_DBG_G_REGISTER`` with a pointer to this structure. On success 66 selects the nth non-sub-device chip on the TV card. The number zero 67 always selects the host chip, e. g. the chip connected to the PCI or USB 72 selects the nth sub-device. 83 We recommended the v4l2-dbg utility over calling these ioctls directly. 84 It is available from the LinuxTV v4l-dvb repository; see [all …]
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/Documentation/powerpc/ |
D | vcpudispatch_stats.rst | 1 .. SPDX-License-Identifier: GPL-2.0 10 on their associated physical processor chip. However, under certain 11 scenarios, vcpus may be dispatched on a different processor chip (away 31 2. number of times this vcpu was dispatched on the same processor as last 33 3. number of times this vcpu was dispatched on a different processor core 34 as last time, but within the same chip 35 4. number of times this vcpu was dispatched on a different chip 36 5. number of times this vcpu was dispatches on a different socket/drawer 42 6. number of times this vcpu was dispatched in its home node (chip) 68 statistics were enabled. 4126 of those dispatches were on the same [all …]
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/Documentation/devicetree/bindings/net/nfc/ |
D | nfcmrvl.txt | 4 - compatible: Should be: 5 - "marvell,nfc-uart" or "mrvl,nfc-uart" for UART devices 6 - "marvell,nfc-i2c" for I2C devices 7 - "marvell,nfc-spi" for SPI devices 10 - pinctrl-names: Contains only one value - "default". 11 - pintctrl-0: Specifies the pin control groups used for this controller. 12 - reset-n-io: Output GPIO pin used to reset the chip (active low). 13 - hci-muxed: Specifies that the chip is muxing NCI over HCI frames. 15 Optional UART-based chip specific properties: 16 - flow-control: Specifies that the chip is using RTS/CTS. [all …]
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/Documentation/scsi/ |
D | 53c700.rst | 1 .. SPDX-License-Identifier: GPL-2.0 10 This driver supports the 53c700 and 53c700-66 chips. It also supports 12 does sync (-66 and 710 only), disconnects and tag command queueing. 29 define if the chipset must be supported in little endian mode on a big 30 endian architecture (used for the 700 on parisc). 33 Using the Chip Core Driver 36 In order to plumb the 53c700 chip core driver into a working SCSI 37 driver, you need to know three things about the way the chip is wired 45 the SCSI Id from the card bios or whether the chip is wired for 54 asynchronous dividers for the chip. As a general rule of thumb, [all …]
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/Documentation/core-api/ |
D | genericirq.rst | 7 :Copyright: |copy| 2005-2010: Thomas Gleixner 8 :Copyright: |copy| 2005-2006: Ingo Molnar 18 hardware details, so they can be used on different platforms without 29 __do_IRQ() super-handler, which is able to deal with every type of 36 - Level type 38 - Edge type 40 - Simple type 44 - Fast EOI type 46 In the SMP world of the __do_IRQ() super-handler another type was 49 - Per CPU type [all …]
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/Documentation/driver-api/ |
D | edac.rst | 5 ---------------------------------------- 8 *sockets, *socket sets*, *banks*, *rows*, *chip-select rows*, *channels*, 18 The individual DRAM chips on a memory stick. These devices commonly 32 A physical connector on the motherboard that accepts a single memory 33 stick. Also called as "slot" on several datasheets. 43 It is typically the highest hierarchy on a Fully-Buffered DIMM memory 50 of correcting more errors than on single mode. 52 * Single-channel 55 only. E. g. if the data is 64 bits-wide, the data flows to the CPU using 57 memories. FB-DIMM and RAMBUS use a different concept for channel, so [all …]
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/Documentation/misc-devices/ |
D | bh1770glc.rst | 1 .. SPDX-License-Identifier: GPL-2.0 9 - ROHM BH1770GLC 10 - OSRAM SFH7770 19 ----------- 21 ALS and proximity parts operates on their own, but they shares common I2C 22 interface and interrupt logic. In principle they can run on their own, 25 ALS produces 16 bit lux values. The chip contains interrupt logic to produce 28 Proximity part contains IR-led driver up to 3 IR leds. The chip measures 35 Proximity low interrupt doesn't exists in the chip. This is simulated 41 Chip state is controlled via runtime pm framework when enabled in config. [all …]
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D | apds990x.rst | 1 .. SPDX-License-Identifier: GPL-2.0 17 ----------- 25 using clear channel only. Lux value and the threshold level on the HW 44 Driver controls chip operational state using pm_runtime framework. 45 Voltage regulators are controlled based on chip operational state. 48 ----- 52 RO - shows detected chip type and version 55 RW - enable / disable chip. Uses counting logic 57 1 enables the chip 58 0 disables the chip [all …]
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/Documentation/devicetree/bindings/spi/ |
D | spi-sprd-adi.txt | 3 ADI is the abbreviation of Anolog-Digital interface, which is used to access 4 analog chip (such as PMIC) from digital chip. ADI controller follows the SPI 9 48 hardware channels to access analog chip. For 2 software read/write channels, 10 users should set ADI registers to access analog chip. For hardware channels, 12 which means we can just link one analog chip address to one hardware channel, 13 then users can access the mapped analog chip address by this hardware channel 16 Thus we introduce one property named "sprd,hw-channels" to configure hardware 19 the analog chip address where user want to access by hardware components. 21 Since we have multi-subsystems will use unique ADI to access analog chip, when 34 - compatible: Should be "sprd,sc9860-adi". [all …]
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/Documentation/devicetree/bindings/rtc/ |
D | isil,isl12057.txt | 1 Intersil ISL12057 I2C RTC/Alarm chip 8 ("wakeup-source") to handle the specific use-case found 9 on at least three in-tree users of the chip (NETGEAR ReadyNAS 102, 104 10 and 2120 ARM-based NAS); On those devices, the IRQ#2 pin of the chip 15 be set when the IRQ#2 pin of the chip is not connected to the SoC but 20 - "compatible": must be "isil,isl12057" 21 - "reg": I2C bus address of the device 25 - "wakeup-source": mark the chip as a wakeup source, independently of 38 that the pinctrl-related properties below are given for completeness and 39 may not be required or may be different depending on your system or [all …]
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/Documentation/devicetree/bindings/devfreq/event/ |
D | exynos-nocp.txt | 2 * Samsung Exynos NoC (Network on Chip) Probe device 4 The Samsung Exynos542x SoC has NoC (Network on Chip) Probe for NoC bus. 6 that the Network on Chip (NoC) probes detects are transported over 8 capture packets with header or data on the data request response network, 14 - compatible: Should be "samsung,exynos5420-nocp" 15 - reg: physical base address of each NoC Probe and length of memory mapped region. 18 - clock-names : the name of clock used by the NoC Probe, "nocp" 19 - clocks : phandles for clock specified in "clock-names" property 24 compatible = "samsung,exynos5420-nocp";
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/Documentation/networking/device_drivers/wan/ |
D | z8530book.rst | 10 The Z85x30 family synchronous/asynchronous controller chips are used on 13 services using this chip. 25 on the chip (each chip has two channels). 28 chip is interface to the I/O and interrupt facilities of the host 34 The DMA mode supports the chip when it is configured to use dual DMA 35 channels on an ISA bus. The better cards tend to support this mode of 38 noting here that many PC machines hang or crash when the chip is driven 54 Having identified the chip you need to fill in a struct z8530_dev, 55 which describes each chip. This object must exist until you finally 58 interrupt number of the chip. (Each chip has a single interrupt source [all …]
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/Documentation/devicetree/bindings/display/bridge/ |
D | adi,adv7511.txt | 2 ------------------------------------------------ 11 - compatible: Should be one of: 18 - reg: I2C slave addresses 21 I2C address and acts as a standard slave device on the I2C bus. The main 28 arrangement of components on the data bus. The combination of the following 32 - adi,input-depth: Number of bits per color component at the input (8, 10 or 34 - adi,input-colorspace: The input color space, one of "rgb", "yuv422" or 36 - adi,input-clock: The input clock type, one of "1x" (one clock cycle per 38 data driven on both edges). 43 - adi,input-style: The input components arrangement variant (1, 2 or 3), as [all …]
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/Documentation/devicetree/bindings/powerpc/fsl/ |
D | pmc.txt | 4 - compatible: "fsl,<chip>-pmc". 6 "fsl,mpc8349-pmc" should be listed for any chip whose PMC is 7 compatible. "fsl,mpc8313-pmc" should also be listed for any chip 8 whose PMC is compatible, and implies deep-sleep capability. 10 "fsl,mpc8548-pmc" should be listed for any chip whose PMC is 11 compatible. "fsl,mpc8536-pmc" should also be listed for any chip 12 whose PMC is compatible, and implies deep-sleep capability. 14 "fsl,mpc8641d-pmc" should be listed for any chip whose PMC is 15 compatible; all statements below that apply to "fsl,mpc8548-pmc" also 16 apply to "fsl,mpc8641d-pmc". [all …]
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/Documentation/devicetree/bindings/net/ |
D | gpmc-eth.txt | 1 Device tree bindings for Ethernet chip connected to TI GPMC 4 General-Purpose Memory Controller can be used to connect Pseudo-SRAM devices 12 Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt 18 Child nodes need to specify the GPMC bus address width using the "bank-width" 20 specify the I/O registers address width. Even when the GPMC has a maximum 16-bit 21 address width, it supports devices with 32-bit word registers. 22 For example with an SMSC LAN911x/912x controller connected to the TI GPMC on an 23 OMAP2+ board, "bank-width = <2>;" and "reg-io-width = <4>;". 26 - bank-width: Address width of the device in bytes. GPMC supports 8-bit 27 and 16-bit devices and so must be either 1 or 2 bytes. [all …]
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/Documentation/sound/ |
D | alsa-configuration.rst | 2 Advanced Linux Sound Architecture - Driver Configuration guide 16 If you want to support the WaveTable functionality on cards such as 21 and "Debug" options. To check for memory leaks, turn on "Debug memory" 38 ---------- 47 limiting card index for auto-loading (1-8); 49 For auto-loading more than one card, specify this option 50 together with snd-card-X aliases. 63 Module snd-pcm-oss 64 ------------------ 86 regarding opening the device. When this option is non-zero, [all …]
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/Documentation/leds/ |
D | leds-lp3944.rst | 5 * National Semiconductor LP3944 Fun-light Chip 21 ----------- 22 The LP3944 is a helper chip that can drive up to 8 leds, with two programmable 29 - period: 31 - duty cycle: 32 percentage of the period the led is on, from 0 to 100 37 LP3944 can be found on Motorola A910 smartphone, where it drives the rgb 42 ----- 43 The chip is used mainly in embedded contexts, so this driver expects it is 46 To register the chip at address 0x60 on adapter 0, set the platform data [all …]
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/Documentation/devicetree/bindings/arm/ |
D | atmel-sysregs.txt | 4 - compatible: Should be "atmel,sama5d2-chipid" 5 - reg : Should contain registers location and length 8 - compatible: Should be "atmel,at91sam9260-pit" 9 - reg: Should contain registers location and length 10 - interrupts: Should contain interrupt for the PIT which is the IRQ line 14 - compatible: Should be "microchip,sam9x60-pit64b" 15 - reg: Should contain registers location and length 16 - interrupts: Should contain interrupt for PIT64B timer 17 - clocks: Should contain the available clock sources for PIT64B timer. 20 - compatible: Should be "atmel,at91rm9200-st", "syscon", "simple-mfd" [all …]
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/Documentation/hwmon/ |
D | amc6821.rst | 19 ----------- 21 This driver implements support for the Texas Instruments amc6821 chip. 22 The chip has one on-chip and one remote temperature sensor and one pwm fan 29 temp1_input ro on-chip temperature 55 combination of the on-chip temperature and 56 remote-sensor temperature, 67 temp1_auto_point2_temp rw The low-temperature limit of the proportional 76 which depend on temp1_auto_point2_temp and 84 temp2_auto_point2_temp rw The low-temperature limit of the proportional 92 values which depend on temp2_auto_point2_temp [all …]
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D | w83793.rst | 10 Addresses scanned: I2C 0x2c - 0x2f 15 - Yuan Mu (Winbond Electronics) 16 - Rudolf Marek <r.marek@assembler.cz> 20 ----------------- 26 settings. Use 'reset=1' to reset the chip when loading this module. 30 a certain chip. Typical usage is `force_subclients=0,0x2f,0x4a,0x4b` 31 to force the subclients of chip 0x2f on bus 0 to i2c addresses 36 ----------- 43 (automatic fan speed control) on all temperature/PWM combinations, 2 44 sets of 6-pin CPU VID input. [all …]
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D | adm1025.rst | 10 Addresses scanned: I2C 0x2c - 0x2e 18 Addresses scanned: I2C 0x2c - 0x2d 24 * Only two possible addresses (0x2c - 0x2d). 29 - Chen-Yuan Wu <gwu@esoft.com>, 30 - Jean Delvare <jdelvare@suse.de> 33 ----------- 36 monitor for microprocessor-based systems, providing measurement and limit 39 the processor core voltage. The ADM1025 can monitor a sixth power-supply 41 remote temperature-sensing diode and an on-chip temperature sensor allows 44 One specificity of this chip is that the pin 11 can be hardwired in two [all …]
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D | adm1275.rst | 10 Addresses scanned: - 12 Datasheet: www.analog.com/static/imported-files/data_sheets/ADM1075.pdf 18 Addresses scanned: - 20 Datasheet: www.analog.com/static/imported-files/data_sheets/ADM1272.pdf 26 Addresses scanned: - 28 Datasheet: www.analog.com/static/imported-files/data_sheets/ADM1275.pdf 34 Addresses scanned: - 36 Datasheet: www.analog.com/static/imported-files/data_sheets/ADM1276.pdf 42 Addresses scanned: - 44 Datasheet: www.analog.com/static/imported-files/data_sheets/ADM1278.pdf [all …]
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/Documentation/devicetree/bindings/mtd/ |
D | gpmc-nor.txt | 3 NOR flash connected to the TI GPMC (found on OMAP boards) are represented as 8 Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt 11 - bank-width: Width of NOR flash in bytes. GPMC supports 8-bit and 12 16-bit devices and so must be either 1 or 2 bytes. 13 - compatible: Documentation/devicetree/bindings/mtd/mtd-physmap.txt 14 - gpmc,cs-on-ns: Chip-select assertion time 15 - gpmc,cs-rd-off-ns: Chip-select de-assertion time for reads 16 - gpmc,cs-wr-off-ns: Chip-select de-assertion time for writes 17 - gpmc,oe-on-ns: Output-enable assertion time 18 - gpmc,oe-off-ns: Output-enable de-assertion time [all …]
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/Documentation/devicetree/bindings/hwmon/ |
D | g762.txt | 5 - "compatible": must be either "gmt,g762" or "gmt,g763" 6 - "reg": I2C bus address of the device 7 - "clocks": a fixed clock providing input clock frequency 8 on CLK pin of the chip. 12 - "fan_startv": fan startup voltage. Accepted values are 0, 1, 2 and 3. 15 - "pwm_polarity": pwm polarity. Accepted values are 0 (positive duty) 18 - "fan_gear_mode": fan gear mode. Supported values are 0, 1 and 2. 21 unmodified (e.g. u-boot installed value). 23 Additional information on operational parameters for the device is available 25 at http://natisbad.org/NAS/refs/GMT_EDS-762_763-080710-0.2.pdf. [all …]
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