/arch/mips/netlogic/common/ |
D | reset.S | 60 mfcr t1, t0 63 or t1, t1, t2 64 mtcr t1, t0 67 mfcr t1, t0 68 ori t1, 0x1000 /* Enable Icache partitioning */ 69 mtcr t1, t0 72 lui t1, 0x0100 /* Disable BRU accepting ALU ops */ 73 mtcr t1, t0 83 li t1, (1 << 29) /* ELPA bit */ 84 or t0, t1 [all …]
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D | smpboot.S | 62 PTR_LA t1, nlm_reset_entry 64 dsubu t2, t1 76 move t1, zero 78 ori t1, ST0_KX 80 mtc0 t1, CP0_STATUS 81 PTR_LA t1, nlm_next_sp 82 PTR_L sp, 0(t1) 83 PTR_LA t1, nlm_next_gp 84 PTR_L gp, 0(t1) 111 ADDIU t1, t3, BOOT_CPU_READY [all …]
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/arch/arm/crypto/ |
D | sha512-armv4.pl | 74 $t1="r10"; 99 mov $t1,$Ehi,lsr#14 103 eor $t1,$t1,$Elo,lsl#18 106 eor $t1,$t1,$Ehi,lsr#18 108 eor $t1,$t1,$Elo,lsl#14 110 eor $t1,$t1,$Elo,lsr#9 112 eor $t1,$t1,$Ehi,lsl#23 @ Sigma1(e) 115 adc $Thi,$Thi,$t1 @ T += Sigma1(e) 116 ldr $t1,[sp,#$Foff+4] @ f.hi 124 eor $t1,$t1,$t3 [all …]
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D | sha256-armv4.pl | 52 $len="r2"; $t1="r2"; 76 @ ldr $t1,[$inp],#4 @ $i 84 rev $t1,$t1 87 @ ldrb $t1,[$inp,#3] @ $i 91 orr $t1,$t1,$t2,lsl#8 93 orr $t1,$t1,$t0,lsl#16 98 orr $t1,$t1,$t2,lsl#24 104 add $h,$h,$t1 @ h+=X[i] 105 str $t1,[sp,#`$i%16`*4] 106 eor $t1,$f,$g [all …]
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/arch/mips/kernel/ |
D | cps-vec.S | 179 1: PTR_L t1, VPEBOOTCFG_PC(v1) 182 jr t1 242 PTR_LA t1, 1f 243 jr.hb t1 273 sll t1, ta1, VPECONF0_XTC_SHIFT 274 or t0, t0, t1 311 li t1, COREBOOTCFG_SIZE 312 mul t0, t0, t1 313 PTR_LA t1, mips_cps_core_bootcfg 314 PTR_L t1, 0(t1) [all …]
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D | octeon_switch.S | 27 mfc0 t1, CP0_STATUS 28 LONG_S t1, THREAD_STATUS(a0) 42 li t1, -32768 /* Base address of CVMSEG */ 47 LONG_L t8, 0(t1) /* Load from CVMSEG */ 49 LONG_L t9, LONGSIZE(t1)/* Load from CVMSEG */ 50 LONG_ADDU t1, LONGSIZE*2 /* Increment loc in CVMSEG */ 78 set_saved_sp t0, t1, t2 80 mfc0 t1, CP0_STATUS /* Do we really need this? */ 82 and t1, a3 86 or a2, t1 [all …]
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D | bmips_5xxx_init.S | 30 addu t1, kva, size ; \ 34 addiu t1, t1, -1 ; \ 35 and t1, t2 ; \ 37 bne t0, t1, 9b ; \ 421 li t1, 0x4 422 or t0, t1 427 li t1, 0x4 428 or t0, t1 433 li t1, 0x4 434 or t0, t1 [all …]
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D | r2300_switch.S | 34 mfc0 t1, CP0_STATUS 35 sw t1, THREAD_STATUS(a0) 52 addiu t1, $28, _THREAD_SIZE - 32 53 sw t1, kernelsp 55 mfc0 t1, CP0_STATUS /* Do we really need this? */ 57 and t1, a3 61 or a2, t1
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D | head.S | 103 li t1, 0xd00dfeed 105 li t1, 0xedfe0dd0 108 beq t0, t1, dtb_found 110 li t1, -2 112 beq a0, t1, dtb_found 116 PTR_LA t1, __dtb_end 117 bne t1, t2, dtb_found 125 PTR_LA t1, __bss_stop - LONGSIZE 129 bne t0, t1, 1b 149 set_saved_sp sp, t0, t1 [all …]
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/arch/csky/abiv2/ |
D | strcmp.S | 13 andi t1, a0, 0x3 14 bnez t1, 5f 19 ldw t1, (a1, 0) 21 cmpne t0, t1 29 ldw t1, (a1, 4) 30 cmpne t0, t1 36 ldw t1, (a1, 8) 37 cmpne t0, t1 43 ldw t1, (a1, 12) 44 cmpne t0, t1 [all …]
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/arch/mips/include/asm/sibyte/ |
D | board.h | 29 #define setleds(t0, t1, c0, c1, c2, c3) \ 31 li t1, c0; \ 32 sb t1, 0x18(t0); \ 33 li t1, c1; \ 34 sb t1, 0x10(t0); \ 35 li t1, c2; \ 36 sb t1, 0x08(t0); \ 37 li t1, c3; \ 38 sb t1, 0x00(t0) 40 #define setleds(t0, t1, c0, c1, c2, c3)
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/arch/alpha/lib/ |
D | stxcpy.S | 49 mskqh t1, a1, t3 # e0 : 50 ornot t1, t2, t2 # .. e1 : 53 or t0, t3, t1 # e0 : 61 stq_u t1, 0(a0) # e0 : 63 ldq_u t1, 0(a1) # e0 : 65 cmpbge zero, t1, t8 # e0 (stall) 85 zapnot t1, t6, t1 # e0 : clear src bytes >= null 88 or t0, t1, t1 # e1 : 90 1: stq_u t1, 0(a0) # e0 : 109 ldq_u t1, 0(a1) # e0 : load first src word [all …]
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D | ev6-stxcpy.S | 60 mskqh t1, a1, t3 # U : 61 ornot t1, t2, t2 # E : (stall) 65 or t0, t3, t1 # E : (stall) 74 stq_u t1, 0(a0) # L : 79 ldq_u t1, 0(a1) # L : Latency=3 81 cmpbge zero, t1, t8 # E : (3 cycle stall) 100 zapnot t1, t6, t1 # U : clear src bytes >= null (stall) 104 or t0, t1, t1 # E : (stall) 108 1: stq_u t1, 0(a0) # L : 129 ldq_u t1, 0(a1) # L : load first src word [all …]
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D | stxncpy.S | 57 mskqh t1, a1, t3 # e0 : 58 ornot t1, t2, t2 # .. e1 : 96 ldq_u t1, 0(a0) # e0 : 101 zap t1, t8, t1 # .. e1 : clear dst bytes <= null 102 or t0, t1, t0 # e1 : 122 xor a0, a1, t1 # e0 : 124 and t1, 7, t1 # e0 : 131 bne t1, $unaligned # .. e1 : 135 ldq_u t1, 0(a1) # e0 : load first src word 162 or t1, t4, t1 # e1 : first aligned src word complete [all …]
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D | strrchr.S | 33 cmpbge zero, t0, t1 # .. e1 : bits set iff byte == zero 39 andnot t1, t4, t1 # .. e1 : clear garbage from null test 41 bne t1, $eos # .. e1 : did we already hit the terminator? 50 cmpbge zero, t0, t1 # .. e1 : bits set iff byte == zero 52 beq t1, $loop # .. e1 : if we havnt seen a null, loop 56 negq t1, t4 # e0 : isolate first null byte match 57 and t1, t4, t4 # e1 : 74 and t8, 0xcc, t1 # .. e1 : 75 cmovne t1, t1, t8 # e0 : 76 cmovne t1, 2, t1 # .. e1 : [all …]
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D | ev6-stxncpy.S | 68 mskqh t1, a1, t3 # U : 69 ornot t1, t2, t2 # E : (stall) 122 ldq_u t1, 0(a0) # L : 127 zap t1, t8, t1 # .. e1 : clear dst bytes <= null 128 or t0, t1, t0 # e1 : (stall) 154 xor a0, a1, t1 # E : 156 and t1, 7, t1 # E : (stall) 165 bne t1, $unaligned # U : 167 ldq_u t1, 0(a1) # L : load first src word 202 or t1, t4, t1 # E : first aligned src word complete (stall) [all …]
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/arch/mips/dec/ |
D | int-handler.S | 133 mfc0 t1,CP0_STATUS 138 and t0,t1 # isolate allowed ones 150 # open coded PTR_LA t1, cpu_mask_nr_tbl 152 # open coded la t1, cpu_mask_nr_tbl 153 lui t1, %hi(cpu_mask_nr_tbl) 154 addiu t1, %lo(cpu_mask_nr_tbl) 214 2: lw t2,(t1) 218 addu t1,2*PTRSIZE # delay slot 223 lw a0,%lo(-PTRSIZE)(t1) 239 li t1,CAUSEF_IP>>CAUSEB_IP # mask [all …]
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/arch/mips/net/ |
D | bpf_jit_asm.S | 64 PTR_ADDU t1, $r_skb_data, offset 66 lw $r_A, 0(t1) 74 srl t1, $r_A, 24 76 or t0, t0, t1 78 andi t1, $r_A, 0xff00 80 sll t1, t1, 8 81 or $r_A, t0, t1 93 PTR_ADDU t1, $r_skb_data, offset 94 lhu $r_A, 0(t1) 100 srl t1, $r_A, 8 [all …]
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/arch/alpha/include/uapi/asm/ |
D | swab.h | 27 __u64 t0, t1, t2, t3; in __arch_swab32() local 30 t1 = __kernel_inswl(x, 3); /* t1 : 000000CCDD000000 */ in __arch_swab32() 31 t1 |= t0; /* t1 : 000000CCDDAABBCC */ in __arch_swab32() 32 t2 = t1 >> 16; /* t2 : 0000000000CCDDAA */ in __arch_swab32() 33 t0 = t1 & 0xFF00FF00; /* t0 : 00000000DD00BB00 */ in __arch_swab32() 35 t1 = t0 + t3; /* t1 : ssssssssDDCCBBAA */ in __arch_swab32() 37 return t1; in __arch_swab32()
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/arch/mips/include/asm/mach-cavium-octeon/ |
D | kernel-entry-init.h | 47 and t1, v1, 0xfff8 48 xor t1, t1, 0x9000 # 63-P1 49 beqz t1, 4f 50 and t1, v1, 0xfff8 51 xor t1, t1, 0x9008 # 63-P2 52 beqz t1, 4f 53 and t1, v1, 0xfff8 54 xor t1, t1, 0x9100 # 68-P1 55 beqz t1, 4f 56 and t1, v1, 0xff00 [all …]
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/arch/mips/include/asm/mach-ip27/ |
D | kernel-entry-init.h | 37 dsll t1, NASID_SHFT # Shift text nasid into place 39 or t1, t1, t0 # Physical load address of kernel text 41 dsrl t1, 12 # 4K pfn 43 dsll t1, 6 # Get pfn into place 46 or t0, t0, t1 68 GET_NASID_ASM t1 69 move t2, t1 # text and data are here 77 GET_NASID_ASM t1 80 dsll t1, NASID_SHFT 81 or t0, t0, t1 [all …]
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/arch/parisc/lib/ |
D | lusercopy.S | 143 t1 = r19 define 151 a1 = t1 169 extru t0,31,2,t1 170 cmpib,<>,n 0,t1,.Lunaligned_copy 174 extru t0,31,3,t1 175 cmpib,<>,n 0,t1,.Lalign_loop32 179 extru dst,31,3,t1 180 cmpib,=,n 0,t1,.Lcopy_loop_16_start 181 20: ldb,ma 1(srcspc,src),t1 182 21: stb,ma t1,1(dstspc,dst) [all …]
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/arch/mips/include/asm/ |
D | pm.h | 65 la t1, mips_static_suspend_state 76 LONG_S k0, SSS_SEGCTL0(t1) 78 LONG_S k0, SSS_SEGCTL1(t1) 80 LONG_S k0, SSS_SEGCTL2(t1) 83 LONG_S sp, SSS_SP(t1) 94 LONG_L k0, SSS_SEGCTL0(t1) 96 LONG_L k0, SSS_SEGCTL1(t1) 98 LONG_L k0, SSS_SEGCTL2(t1) 103 LONG_L sp, SSS_SP(t1) 111 la t1, __wback_cache_all [all …]
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/arch/mips/alchemy/common/ |
D | sleeper.S | 55 la t1, __flush_cache_all 56 lw t0, 0(t1) 135 2: lw t1, 0x0850(a0) /* mem_sdstat */ 136 and t2, t1, t0 143 lw t1, 0x0840(a0) /* mem_sdconfiga */ 144 and t1, t0, t1 /* clear CE[1:0] */ 145 sw t1, 0x0840(a0) /* mem_sdconfiga */ 159 la t1, 4f 160 subu t2, t1, t0 195 li t1, (1 << 7 | 0x3F) [all …]
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/arch/x86/crypto/ |
D | glue_helper-asm-avx.S | 44 #define load_ctr_8way(iv, bswap, x0, x1, x2, x3, x4, x5, x6, x7, t0, t1, t2) \ argument 47 vmovdqa bswap, t1; \ 51 vpshufb t1, x7, x0; \ 55 vpshufb t1, x7, x1; \ 57 vpshufb t1, x7, x2; \ 59 vpshufb t1, x7, x3; \ 61 vpshufb t1, x7, x4; \ 63 vpshufb t1, x7, x5; \ 65 vpshufb t1, x7, x6; \ 68 vpshufb t1, x7, x7; \ [all …]
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