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Searched refs:wrmsrl (Results 1 – 25 of 64) sorted by relevance

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/arch/x86/hyperv/
Dhv_init.c114 wrmsrl(HV_X64_MSR_VP_ASSIST_PAGE, val); in hv_cpu_init()
141 wrmsrl(HV_X64_MSR_TSC_EMULATION_STATUS, *(u64 *)&emu_status); in hyperv_stop_tsc_emulation()
189 wrmsrl(HV_X64_MSR_REENLIGHTENMENT_CONTROL, *((u64 *)&re_ctrl)); in set_hv_tscchange_cb()
190 wrmsrl(HV_X64_MSR_TSC_EMULATION_CONTROL, *((u64 *)&emu_ctrl)); in set_hv_tscchange_cb()
205 wrmsrl(HV_X64_MSR_REENLIGHTENMENT_CONTROL, *(u64 *)&re_ctrl); in clear_hv_tscchange_cb()
227 wrmsrl(HV_X64_MSR_VP_ASSIST_PAGE, 0); in hv_cpu_die()
246 wrmsrl(HV_X64_MSR_REENLIGHTENMENT_CONTROL, *((u64 *)&re_ctrl)); in hv_cpu_die()
286 wrmsrl(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64); in hv_suspend()
305 wrmsrl(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64); in hv_resume()
404 wrmsrl(HV_X64_MSR_GUEST_OS_ID, guest_id); in hyperv_init()
[all …]
/arch/x86/oprofile/
Dop_model_amd.c156 wrmsrl(MSR_AMD64_IBSFETCHCTL, ctl); in op_amd_handle_ibs()
185 wrmsrl(MSR_AMD64_IBSOPCTL, ctl); in op_amd_handle_ibs()
211 wrmsrl(MSR_AMD64_IBSFETCHCTL, val); in op_amd_start_ibs()
248 wrmsrl(MSR_AMD64_IBSOPCTL, val); in op_amd_start_ibs()
259 wrmsrl(MSR_AMD64_IBSFETCHCTL, 0); in op_amd_stop_ibs()
263 wrmsrl(MSR_AMD64_IBSOPCTL, 0); in op_amd_stop_ibs()
282 wrmsrl(msrs->controls[i].addr, val); in op_mux_switch_ctrl()
356 wrmsrl(msrs->controls[i].addr, val); in op_amd_setup_ctrs()
361 wrmsrl(msrs->counters[i].addr, -1LL); in op_amd_setup_ctrs()
371 wrmsrl(msrs->counters[i].addr, -(u64)reset_value[virt]); in op_amd_setup_ctrs()
[all …]
Dop_model_ppro.c103 wrmsrl(msrs->controls[i].addr, val); in ppro_setup_ctrs()
108 wrmsrl(msrs->counters[i].addr, -1LL); in ppro_setup_ctrs()
115 wrmsrl(msrs->counters[i].addr, -reset_value[i]); in ppro_setup_ctrs()
119 wrmsrl(msrs->controls[i].addr, val); in ppro_setup_ctrs()
140 wrmsrl(msrs->counters[i].addr, -reset_value[i]); in ppro_check_ctrs()
167 wrmsrl(msrs->controls[i].addr, val); in ppro_start()
183 wrmsrl(msrs->controls[i].addr, val); in ppro_stop()
/arch/x86/include/asm/
Dmshyperv.h18 wrmsrl(HV_X64_MSR_STIMER0_COUNT + (2*timer), tick)
20 wrmsrl(HV_X64_MSR_STIMER0_CONFIG + (2*timer), val)
23 #define hv_set_simp(val) wrmsrl(HV_X64_MSR_SIMP, val)
26 #define hv_set_siefp(val) wrmsrl(HV_X64_MSR_SIEFP, val)
29 #define hv_set_synic_state(val) wrmsrl(HV_X64_MSR_SCONTROL, val)
33 #define hv_signal_eom() wrmsrl(HV_X64_MSR_EOM, 0)
38 wrmsrl(HV_X64_MSR_SINT0 + int_num, val)
51 wrmsrl(HV_X64_MSR_REFERENCE_TSC, val)
Dvirtext.h115 wrmsrl(MSR_VM_HSAVE_PA, 0); in cpu_svm_disable()
130 wrmsrl(MSR_EFER, efer & ~EFER_SVME); in cpu_svm_disable()
Dfsgsbase.h73 wrmsrl(MSR_FS_BASE, fsbase); in x86_fsbase_write_cpu()
/arch/x86/events/intel/
Duncore_nhmex.c202 wrmsrl(NHMEX_U_MSR_PMON_GLOBAL_CTL, NHMEX_U_PMON_GLOBAL_EN_ALL); in nhmex_uncore_msr_init_box()
207 wrmsrl(NHMEX_U_MSR_PMON_GLOBAL_CTL, 0); in nhmex_uncore_msr_exit_box()
221 wrmsrl(msr, config); in nhmex_uncore_msr_disable_box()
236 wrmsrl(msr, config); in nhmex_uncore_msr_enable_box()
242 wrmsrl(event->hw.config_base, 0); in nhmex_uncore_msr_disable_event()
250 wrmsrl(hwc->config_base, NHMEX_PMON_CTL_EN_BIT0); in nhmex_uncore_msr_enable_event()
252 wrmsrl(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT22); in nhmex_uncore_msr_enable_event()
254 wrmsrl(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT0); in nhmex_uncore_msr_enable_event()
384 wrmsrl(reg1->reg, reg1->config); in nhmex_bbox_msr_enable_event()
385 wrmsrl(reg1->reg + 1, reg2->config); in nhmex_bbox_msr_enable_event()
[all …]
Duncore_snb.c146 wrmsrl(hwc->config_base, hwc->config | SNB_UNC_CTL_EN); in snb_uncore_msr_enable_event()
148 wrmsrl(hwc->config_base, SNB_UNC_CTL_EN); in snb_uncore_msr_enable_event()
153 wrmsrl(event->hw.config_base, 0); in snb_uncore_msr_disable_event()
159 wrmsrl(SNB_UNC_PERF_GLOBAL_CTL, in snb_uncore_msr_init_box()
166 wrmsrl(SNB_UNC_PERF_GLOBAL_CTL, in snb_uncore_msr_enable_box()
173 wrmsrl(SNB_UNC_PERF_GLOBAL_CTL, 0); in snb_uncore_msr_exit_box()
258 wrmsrl(SKL_UNC_PERF_GLOBAL_CTL, in skl_uncore_msr_init_box()
269 wrmsrl(SKL_UNC_PERF_GLOBAL_CTL, in skl_uncore_msr_enable_box()
276 wrmsrl(SKL_UNC_PERF_GLOBAL_CTL, 0); in skl_uncore_msr_exit_box()
1100 wrmsrl(NHM_UNC_PERF_GLOBAL_CTL, 0); in nhm_uncore_msr_disable_box()
[all …]
Dlbr.c207 wrmsrl(MSR_LBR_SELECT, lbr_select); in __intel_pmu_lbr_enable()
225 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); in __intel_pmu_lbr_enable()
228 wrmsrl(MSR_ARCH_LBR_CTL, lbr_select | ARCH_LBR_CTL_LBREN); in __intel_pmu_lbr_enable()
236 wrmsrl(MSR_ARCH_LBR_CTL, 0); in __intel_pmu_lbr_disable()
242 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); in __intel_pmu_lbr_disable()
250 wrmsrl(x86_pmu.lbr_from + i, 0); in intel_pmu_lbr_reset_32()
258 wrmsrl(x86_pmu.lbr_from + i, 0); in intel_pmu_lbr_reset_64()
259 wrmsrl(x86_pmu.lbr_to + i, 0); in intel_pmu_lbr_reset_64()
261 wrmsrl(x86_pmu.lbr_info + i, 0); in intel_pmu_lbr_reset_64()
268 wrmsrl(MSR_ARCH_LBR_DEPTH, x86_pmu.lbr_nr); in intel_pmu_arch_lbr_reset()
[all …]
Dknc.c164 wrmsrl(MSR_KNC_IA32_PERF_GLOBAL_CTRL, val); in knc_pmu_disable_all()
173 wrmsrl(MSR_KNC_IA32_PERF_GLOBAL_CTRL, val); in knc_pmu_enable_all()
210 wrmsrl(MSR_KNC_IA32_PERF_GLOBAL_OVF_CONTROL, ack); in knc_pmu_ack_status()
Dp6.c145 wrmsrl(MSR_P6_EVNTSEL0, val); in p6_pmu_disable_all()
155 wrmsrl(MSR_P6_EVNTSEL0, val); in p6_pmu_enable_all()
Dpt.c409 wrmsrl(MSR_IA32_RTIT_CTL, ctl); in pt_config_start()
468 wrmsrl(pt_address_ranges[range].msr_a, filter->msr_a); in pt_config_filters()
473 wrmsrl(pt_address_ranges[range].msr_b, filter->msr_b); in pt_config_filters()
492 wrmsrl(MSR_IA32_RTIT_STATUS, 0); in pt_config()
535 wrmsrl(MSR_IA32_RTIT_CTL, ctl); in pt_config_stop()
624 wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, reg); in pt_config_buffer()
630 wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, reg); in pt_config_buffer()
930 wrmsrl(MSR_IA32_RTIT_STATUS, status); in pt_handle_status()
1540 wrmsrl(MSR_IA32_RTIT_CTL, event->hw.config); in intel_pt_handle_vmx()
/arch/x86/xen/
Dsuspend.c44 wrmsrl(MSR_IA32_SPEC_CTRL, this_cpu_read(spec_ctrl)); in xen_vcpu_notify_restore()
62 wrmsrl(MSR_IA32_SPEC_CTRL, 0); in xen_vcpu_notify_suspend()
/arch/x86/power/
Dcpu.c57 wrmsrl(msr->info.msr_no, msr->info.reg.q); in msr_restore_context()
201 wrmsrl(MSR_IA32_MISC_ENABLE, ctxt->misc_enable); in __restore_processor_state()
211 wrmsrl(MSR_EFER, ctxt->efer); in __restore_processor_state()
234 wrmsrl(MSR_GS_BASE, ctxt->kernelmode_gs_base); in __restore_processor_state()
258 wrmsrl(MSR_FS_BASE, ctxt->fs_base); in __restore_processor_state()
259 wrmsrl(MSR_KERNEL_GS_BASE, ctxt->usermode_gs_base); in __restore_processor_state()
293 wrmsrl(MSR_GS_BASE, saved_context.kernelmode_gs_base); in restore_processor_state()
/arch/x86/kernel/cpu/mce/
Dinject.c462 wrmsrl(MSR_IA32_MCG_STATUS, m.mcgstatus); in prepare_msrs()
466 wrmsrl(MSR_AMD64_SMCA_MCx_DESTAT(b), m.status); in prepare_msrs()
467 wrmsrl(MSR_AMD64_SMCA_MCx_DEADDR(b), m.addr); in prepare_msrs()
469 wrmsrl(MSR_AMD64_SMCA_MCx_STATUS(b), m.status); in prepare_msrs()
470 wrmsrl(MSR_AMD64_SMCA_MCx_ADDR(b), m.addr); in prepare_msrs()
473 wrmsrl(MSR_AMD64_SMCA_MCx_MISC(b), m.misc); in prepare_msrs()
474 wrmsrl(MSR_AMD64_SMCA_MCx_SYND(b), m.synd); in prepare_msrs()
476 wrmsrl(MSR_IA32_MCx_STATUS(b), m.status); in prepare_msrs()
477 wrmsrl(MSR_IA32_MCx_ADDR(b), m.addr); in prepare_msrs()
478 wrmsrl(MSR_IA32_MCx_MISC(b), m.misc); in prepare_msrs()
Dintel.c171 wrmsrl(MSR_IA32_MCx_CTL2(bank), val); in cmci_toggle_interrupt_mode()
309 wrmsrl(MSR_IA32_MCx_CTL2(i), val); in cmci_discover()
364 wrmsrl(MSR_IA32_MCx_CTL2(bank), val); in __cmci_disable_bank()
458 wrmsrl(MSR_IA32_MCG_EXT_CTL, val | MCG_EXT_CTL_LMCE_EN); in intel_init_lmce()
470 wrmsrl(MSR_IA32_MCG_EXT_CTL, val); in intel_clear_lmce()
/arch/x86/kernel/cpu/
Dtsx.c39 wrmsrl(MSR_IA32_TSX_CTRL, tsx); in tsx_disable()
58 wrmsrl(MSR_IA32_TSX_CTRL, tsx); in tsx_enable()
Dcommon.c601 wrmsrl(MSR_GS_BASE, cpu_kernelmode_gs_base(cpu)); in load_percpu_segment()
1524 wrmsrl(MSR_FS_BASE, 1); in detect_null_seg_behavior()
1527 wrmsrl(MSR_FS_BASE, old_base); in detect_null_seg_behavior()
1896 wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64); in syscall_init()
1899 wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat); in syscall_init()
1911 wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret); in syscall_init()
1918 wrmsrl(MSR_SYSCALL_MASK, in syscall_init()
2116 wrmsrl(MSR_FS_BASE, 0); in cpu_init()
2117 wrmsrl(MSR_KERNEL_GS_BASE, 0); in cpu_init()
Dintel_epb.c97 wrmsrl(MSR_IA32_ENERGY_PERF_BIAS, (epb & ~EPB_MASK) | val); in intel_epb_restore()
/arch/x86/kernel/
Dkvm.c300 wrmsrl(MSR_KVM_ASYNC_PF_ACK, 1); in DEFINE_IDTENTRY_SYSVEC()
326 wrmsrl(MSR_KVM_STEAL_TIME, (slow_virt_to_phys(st) | KVM_MSR_ENABLED)); in kvm_register_steal_time()
360 wrmsrl(MSR_KVM_ASYNC_PF_INT, HYPERVISOR_CALLBACK_VECTOR); in kvm_guest_cpu_init()
362 wrmsrl(MSR_KVM_ASYNC_PF_EN, pa); in kvm_guest_cpu_init()
375 wrmsrl(MSR_KVM_PV_EOI_EN, pa); in kvm_guest_cpu_init()
387 wrmsrl(MSR_KVM_ASYNC_PF_EN, 0); in kvm_pv_disable_apf()
409 wrmsrl(MSR_KVM_PV_EOI_EN, 0); in kvm_pv_guest_cpu_reboot()
483 wrmsrl(MSR_KVM_PV_EOI_EN, 0); in kvm_guest_cpu_offline()
659 wrmsrl(MSR_KVM_POLL_CONTROL, 0); in kvm_resume()
1024 wrmsrl(MSR_KVM_POLL_CONTROL, 0); in kvm_disable_host_haltpoll()
[all …]
Dtsc_sync.c72 wrmsrl(MSR_IA32_TSC_ADJUST, adj->adjusted); in tsc_verify_tsc_adjust()
144 wrmsrl(MSR_IA32_TSC_ADJUST, 0); in tsc_sanitize_first_cpu()
233 wrmsrl(MSR_IA32_TSC_ADJUST, ref->adjusted); in tsc_store_and_check_tsc_adjust()
529 wrmsrl(MSR_IA32_TSC_ADJUST, cur->adjusted); in check_tsc_sync_target()
Dprocess.c276 wrmsrl(MSR_MISC_FEATURES_ENABLES, msrval); in set_cpuid_faulting()
491 wrmsrl(MSR_AMD64_LS_CFG, msr); in amd_set_core_ssb_state()
508 wrmsrl(MSR_AMD64_LS_CFG, msr); in amd_set_core_ssb_state()
518 wrmsrl(MSR_AMD64_LS_CFG, msr); in amd_set_core_ssb_state()
527 wrmsrl(MSR_AMD64_LS_CFG, msr); in amd_set_core_ssb_state()
537 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, ssbd_tif_to_spec_ctrl(tifn)); in amd_set_ssb_virt_state()
644 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); in __switch_to_xtra()
Dreboot_fixups_32.c30 wrmsrl(MSR_DIVIL_SOFT_RESET, 1ULL); in cs5536_warm_reset()
Dkvmclock.c64 wrmsrl(msr_kvm_wall_clock, slow_virt_to_phys(&wall_clock)); in kvm_get_wallclock()
177 wrmsrl(msr_kvm_system_time, pa); in kvm_register_clock()
/arch/x86/events/zhaoxin/
Dcore.c257 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); in zhaoxin_pmu_disable_all()
262 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, x86_pmu.intel_ctrl); in zhaoxin_pmu_enable_all()
276 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack); in zhaoxin_pmu_ack_status()
298 wrmsrl(hwc->config_base, ctrl_val); in zhaoxin_pmu_disable_fixed()
335 wrmsrl(hwc->config_base, ctrl_val); in zhaoxin_pmu_enable_fixed()

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