Home
last modified time | relevance | path

Searched refs:outb_p (Results 1 – 25 of 95) sorted by relevance

1234

/drivers/watchdog/
Dw83977f_wdt.c73 outb_p(UNLOCK_DATA, IO_INDEX_PORT); in wdt_start()
74 outb_p(UNLOCK_DATA, IO_INDEX_PORT); in wdt_start()
82 outb_p(DEVICE_REGISTER, IO_INDEX_PORT); in wdt_start()
83 outb_p(0x08, IO_DATA_PORT); in wdt_start()
84 outb_p(0xF2, IO_INDEX_PORT); in wdt_start()
85 outb_p(timeoutW, IO_DATA_PORT); in wdt_start()
86 outb_p(0xF3, IO_INDEX_PORT); in wdt_start()
87 outb_p(0x08, IO_DATA_PORT); in wdt_start()
88 outb_p(0xF4, IO_INDEX_PORT); in wdt_start()
89 outb_p(0x00, IO_DATA_PORT); in wdt_start()
[all …]
Dwdt977.c83 outb_p(UNLOCK_DATA, IO_INDEX_PORT); in wdt977_start()
84 outb_p(UNLOCK_DATA, IO_INDEX_PORT); in wdt977_start()
92 outb_p(DEVICE_REGISTER, IO_INDEX_PORT); in wdt977_start()
93 outb_p(0x08, IO_DATA_PORT); in wdt977_start()
94 outb_p(0xF2, IO_INDEX_PORT); in wdt977_start()
95 outb_p(timeoutM, IO_DATA_PORT); in wdt977_start()
96 outb_p(0xF3, IO_INDEX_PORT); in wdt977_start()
97 outb_p(0x00, IO_DATA_PORT); /* another setting is 0E for in wdt977_start()
99 outb_p(0xF4, IO_INDEX_PORT); in wdt977_start()
100 outb_p(0x00, IO_DATA_PORT); in wdt977_start()
[all …]
Dpc87413_wdt.c76 outb_p(SIOCFG2, WDT_INDEX_IO_PORT); in pc87413_select_wdt_out()
81 outb_p(SIOCFG2, WDT_INDEX_IO_PORT); in pc87413_select_wdt_out()
83 outb_p(cr_data, WDT_DATA_IO_PORT); in pc87413_select_wdt_out()
100 outb_p(0x07, WDT_INDEX_IO_PORT); /* Point SWC_LDN (LDN=4) */ in pc87413_enable_swc()
101 outb_p(SWC_LDN, WDT_DATA_IO_PORT); in pc87413_enable_swc()
103 outb_p(0x30, WDT_INDEX_IO_PORT); /* Read Index 0x30 First */ in pc87413_enable_swc()
106 outb_p(0x30, WDT_INDEX_IO_PORT); in pc87413_enable_swc()
107 outb_p(cr_data, WDT_DATA_IO_PORT); /* Index0x30_bit0P1 */ in pc87413_enable_swc()
122 outb_p(0x60, WDT_INDEX_IO_PORT); /* Read Index 0x60 */ in pc87413_get_swc_base_addr()
125 outb_p(0x61, WDT_INDEX_IO_PORT); /* Read Index 0x61 */ in pc87413_get_swc_base_addr()
[all …]
/drivers/i2c/busses/
Di2c-ali1535.c251 outb_p(ALI1535_T_OUT, SMBHSTTYP); in ali1535_transaction()
258 outb_p(0xFF, SMBHSTSTS); in ali1535_transaction()
273 outb_p(temp, SMBHSTSTS); in ali1535_transaction()
277 outb_p(0xFF, SMBHSTPORT); in ali1535_transaction()
329 outb_p(ALI1535_KILL, SMBHSTTYP); in ali1535_transaction()
330 outb_p(0xFF, SMBHSTSTS); in ali1535_transaction()
333 outb_p(ALI1535_T_OUT, SMBHSTTYP); in ali1535_transaction()
334 outb_p(0xFF, SMBHSTSTS); in ali1535_transaction()
362 outb_p(0xFF, SMBHSTSTS); in ali1535_access()
366 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), in ali1535_access()
[all …]
Di2c-ali1563.c80 outb_p(data | HST_STS_BAD, SMB_HST_STS); in ali1563_transaction()
85 outb_p(inb_p(SMB_HST_CNTL2) | HST_CNTL2_START, SMB_HST_CNTL2); in ali1563_transaction()
104 outb_p(HST_CNTL2_KILL, SMB_HST_CNTL2); in ali1563_transaction()
119 outb_p(HST_CNTL1_TIMEOUT, SMB_HST_CNTL1); in ali1563_transaction()
124 outb_p(0x0, SMB_HST_CNTL2); in ali1563_transaction()
145 outb_p(data | HST_STS_BAD, SMB_HST_STS); in ali1563_block_start()
152 outb_p(data | HST_STS_DONE, SMB_HST_STS); in ali1563_block_start()
155 outb_p(inb_p(SMB_HST_CNTL2) | HST_CNTL2_START, SMB_HST_CNTL2); in ali1563_block_start()
193 outb_p(HST_CNTL1_LAST, SMB_HST_CNTL1); in ali1563_block()
201 outb_p(len, SMB_HST_DAT0); in ali1563_block()
[all …]
Di2c-ali15x3.c259 outb_p(ALI15X3_T_OUT, SMBHSTCNT); in ali15x3_transaction()
266 outb_p(0xFF, SMBHSTSTS); in ali15x3_transaction()
280 outb_p(temp, SMBHSTSTS); in ali15x3_transaction()
285 outb_p(0xFF, SMBHSTSTART); in ali15x3_transaction()
341 outb_p(0xFF, SMBHSTSTS); in ali15x3_access()
356 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), in ali15x3_access()
361 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), in ali15x3_access()
364 outb_p(command, SMBHSTCMD); in ali15x3_access()
368 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), in ali15x3_access()
370 outb_p(command, SMBHSTCMD); in ali15x3_access()
[all …]
Di2c-piix4.c300 outb_p(smb_en, SB800_PIIX4_SMB_IDX); in piix4_setup_sb800()
302 outb_p(smb_en + 1, SB800_PIIX4_SMB_IDX); in piix4_setup_sb800()
380 outb_p(SB800_PIIX4_PORT_IDX_SEL, SB800_PIIX4_SMB_IDX); in piix4_setup_sb800()
454 outb_p(temp, SMBHSTSTS); in piix4_transaction()
464 outb_p(inb(SMBHSTCNT) | 0x040, SMBHSTCNT); in piix4_transaction()
500 outb_p(inb(SMBHSTSTS), SMBHSTSTS); in piix4_transaction()
525 outb_p((addr << 1) | read_write, in piix4_access()
530 outb_p((addr << 1) | read_write, in piix4_access()
533 outb_p(command, SMBHSTCMD); in piix4_access()
537 outb_p((addr << 1) | read_write, in piix4_access()
[all …]
Di2c-viapro.c141 outb_p(temp, SMBHSTSTS); in vt596_transaction()
150 outb_p(0x40 | size, SMBHSTCNT); in vt596_transaction()
182 outb_p(temp, SMBHSTSTS); in vt596_transaction()
203 outb_p(command, SMBHSTCMD); in vt596_access()
207 outb_p(command, SMBHSTCMD); in vt596_access()
209 outb_p(data->byte, SMBHSTDAT0); in vt596_access()
213 outb_p(command, SMBHSTCMD); in vt596_access()
215 outb_p(data->word & 0xff, SMBHSTDAT0); in vt596_access()
216 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1); in vt596_access()
221 outb_p(command, SMBHSTCMD); in vt596_access()
[all …]
Di2c-i801.c339 outb_p(status, SMBHSTSTS(priv)); in i801_check_pre()
361 outb_p(status, SMBAUXSTS(priv)); in i801_check_pre()
394 outb_p(SMBHSTCNT_KILL, SMBHSTCNT(priv)); in i801_check_post()
396 outb_p(0, SMBHSTCNT(priv)); in i801_check_post()
404 outb_p(STATUS_FLAGS, SMBHSTSTS(priv)); in i801_check_post()
430 outb_p(SMBAUXSTS_CRCE, SMBAUXSTS(priv)); in i801_check_post()
444 outb_p(status, SMBHSTSTS(priv)); in i801_check_post()
501 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START, in i801_transaction()
517 outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv)); in i801_transaction()
544 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv)); in i801_block_transaction_by_block()
[all …]
Di2c-nforce2.c142 outb_p(NVIDIA_SMB_CTRL_ABORT, NVIDIA_SMB_CTRL); in nforce2_abort()
150 outb_p(NVIDIA_SMB_STATUS_ABRT_STS, NVIDIA_SMB_STATUS_ABRT); in nforce2_abort()
199 outb_p(command, NVIDIA_SMB_CMD); in nforce2_access()
204 outb_p(command, NVIDIA_SMB_CMD); in nforce2_access()
206 outb_p(data->byte, NVIDIA_SMB_DATA); in nforce2_access()
211 outb_p(command, NVIDIA_SMB_CMD); in nforce2_access()
213 outb_p(data->word, NVIDIA_SMB_DATA); in nforce2_access()
214 outb_p(data->word >> 8, NVIDIA_SMB_DATA + 1); in nforce2_access()
220 outb_p(command, NVIDIA_SMB_CMD); in nforce2_access()
229 outb_p(len, NVIDIA_SMB_BCNT); in nforce2_access()
[all …]
/drivers/video/console/
Dvgacon.c291 outb_p(i, VGA_ATT_W); in vgacon_startup()
292 outb_p(i, VGA_ATT_W); in vgacon_startup()
294 outb_p(0x20, VGA_ATT_W); in vgacon_startup()
301 outb_p(color_table[i], VGA_PEL_IW); in vgacon_startup()
302 outb_p(default_red[i], VGA_PEL_D); in vgacon_startup()
303 outb_p(default_grn[i], VGA_PEL_D); in vgacon_startup()
304 outb_p(default_blu[i], VGA_PEL_D); in vgacon_startup()
485 outb_p(VGA_CRTC_CURSOR_START, vga_video_port_reg); in vgacon_set_cursor_size()
487 outb_p(VGA_CRTC_CURSOR_END, vga_video_port_reg); in vgacon_set_cursor_size()
497 outb_p(VGA_CRTC_CURSOR_START, vga_video_port_reg); in vgacon_set_cursor_size()
[all …]
Dmdacon.c114 outb_p(reg, mda_index_port); in write_mda_b()
115 outb_p(val, mda_value_port); in write_mda_b()
126 outb_p(reg, mda_index_port); outb_p(val >> 8, mda_value_port); in write_mda_w()
127 outb_p(reg+1, mda_index_port); outb_p(val & 0xff, mda_value_port); in write_mda_w()
139 outb_p(reg, mda_index_port); in test_mda_b()
315 outb_p(MDA_MODE_VIDEO_EN | MDA_MODE_BLINK_EN, mda_mode_port); in mda_initialize()
316 outb_p(0x00, mda_status_port); in mda_initialize()
317 outb_p(0x00, mda_gfx_port); in mda_initialize()
478 outb_p(0x00, mda_mode_port); /* disable video */ in mdacon_blank()
480 outb_p(MDA_MODE_VIDEO_EN | MDA_MODE_BLINK_EN, in mdacon_blank()
/drivers/clocksource/
Di8253.c59 outb_p(0x00, PIT_MODE); /* latch the count ASAP */ in i8253_read()
65 outb_p(0x34, PIT_MODE); in i8253_read()
66 outb_p(PIT_LATCH & 0xff, PIT_CH0); in i8253_read()
67 outb_p(PIT_LATCH >> 8, PIT_CH0); in i8253_read()
118 outb_p(0x30, PIT_MODE); in pit_shutdown()
121 outb_p(0, PIT_CH0); in pit_shutdown()
122 outb_p(0, PIT_CH0); in pit_shutdown()
132 outb_p(0x38, PIT_MODE); in pit_set_oneshot()
142 outb_p(0x34, PIT_MODE); in pit_set_periodic()
143 outb_p(PIT_LATCH & 0xff, PIT_CH0); /* LSB */ in pit_set_periodic()
[all …]
/drivers/staging/kpc2000/
Dkpc2000_i2c.c128 #undef outb_p
129 #define outb_p(d, a) writeq(d, (void __iomem *)a) macro
147 outb_p(status, SMBHSTSTS(priv)); in i801_check_pre()
169 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL, in i801_check_post()
172 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL), in i801_check_post()
181 outb_p(STATUS_FLAGS, SMBHSTSTS(priv)); in i801_check_post()
200 outb_p(status & STATUS_FLAGS, SMBHSTSTS(priv)); in i801_check_post()
221 outb_p(xact | I801_START, SMBHSTCNT(priv)); in i801_transaction()
233 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv)); in i801_transaction()
251 outb_p(status, SMBHSTSTS(priv)); in i801_wait_hwpec()
[all …]
/drivers/input/serio/
Dct82c710.c87 outb_p(inb_p(CT82C710_STATUS) & ~(CT82C710_ENABLE | CT82C710_INTS_ON), CT82C710_STATUS); in ct82c710_close()
107 outb_p(status, CT82C710_STATUS); in ct82c710_open()
110 outb_p(status, CT82C710_STATUS); in ct82c710_open()
113 outb_p(status, CT82C710_STATUS); /* Enable interrupts */ in ct82c710_open()
118 outb_p(status, CT82C710_STATUS); in ct82c710_open()
133 outb_p(c, CT82C710_DATA); in ct82c710_write()
143 outb_p(0x55, 0x2fa); /* Any value except 9, ff or 36 */ in ct82c710_detect()
144 outb_p(0xaa, 0x3fa); /* Inverse of 55 */ in ct82c710_detect()
145 outb_p(0x36, 0x3fa); /* Address the chip */ in ct82c710_detect()
146 outb_p(0xe4, 0x3fa); /* 390/4; 390 = config address */ in ct82c710_detect()
[all …]
/drivers/net/ethernet/8390/
Daxnet_cs.c219 outb_p(program_seq[i].value, ioaddr + program_seq[i].offset); in get_prom()
421 outb_p(MDIO_DATA_WRITE1, addr); in mdio_sync()
422 outb_p(MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK, addr); in mdio_sync()
434 outb_p(dat, addr); in mdio_read()
435 outb_p(dat | MDIO_SHIFT_CLK, addr); in mdio_read()
438 outb_p(MDIO_ENB_IN, addr); in mdio_read()
440 outb_p(MDIO_ENB_IN | MDIO_SHIFT_CLK, addr); in mdio_read()
453 outb_p(dat, addr); in mdio_write()
454 outb_p(dat | MDIO_SHIFT_CLK, addr); in mdio_write()
457 outb_p(MDIO_ENB_IN, addr); in mdio_write()
[all …]
Dne.c315 outb_p(E8390_NODMA+E8390_PAGE1+E8390_STOP, ioaddr + E8390_CMD); in ne_probe1()
317 outb_p(0xff, ioaddr + 0x0d); in ne_probe1()
318 outb_p(E8390_NODMA+E8390_PAGE0, ioaddr + E8390_CMD); in ne_probe1()
321 outb_p(reg0, ioaddr); in ne_probe1()
322 outb_p(regd, ioaddr + 0x0d); /* Restore the old values. */ in ne_probe1()
361 outb_p(0xff, ioaddr + EN0_ISR); /* Ack all intr. */ in ne_probe1()
387 outb_p(program_seq[i].value, ioaddr + program_seq[i].offset); in ne_probe1()
402 outb_p(DCR_VAL, ioaddr + EN0_DCFG); in ne_probe1()
473 outb_p(0x50, ioaddr + EN0_IMR); /* Enable one interrupt. */ in ne_probe1()
474 outb_p(0x00, ioaddr + EN0_RCNTLO); in ne_probe1()
[all …]
Dpcnet_cs.c353 outb_p(program_seq[i].value, ioaddr + program_seq[i].offset); in get_prom()
409 outb_p(0x01, ioaddr + EN0_DCFG); /* Set word-wide access. */ in get_ax88190()
410 outb_p(0x00, ioaddr + EN0_RSARLO); /* DMA starting at 0x0400. */ in get_ax88190()
411 outb_p(0x04, ioaddr + EN0_RSARHI); in get_ax88190()
412 outb_p(E8390_RREAD+E8390_START, ioaddr + E8390_CMD); in get_ax88190()
771 outb_p(EE_EEP|EE_CS|dataval, ee_addr); in read_eeprom()
772 outb_p(EE_EEP|EE_CS|dataval|EE_CK, ee_addr); in read_eeprom()
777 outb_p(EE_EEP|EE_CS | EE_CK, ee_addr); in read_eeprom()
779 outb_p(EE_EEP|EE_CS, ee_addr); in read_eeprom()
810 outb_p(EE_ASIC|EE_CS|EE_DI|dataval, ee_addr); in write_asic()
[all …]
/drivers/media/radio/
Dradio-rtrack2.c55 outb_p(1, isa->io); in zero()
56 outb_p(3, isa->io); in zero()
57 outb_p(1, isa->io); in zero()
62 outb_p(5, isa->io); in one()
63 outb_p(7, isa->io); in one()
64 outb_p(5, isa->io); in one()
73 outb_p(0xc8, isa->io); in rtrack2_s_frequency()
74 outb_p(0xc9, isa->io); in rtrack2_s_frequency()
75 outb_p(0xc9, isa->io); in rtrack2_s_frequency()
86 outb_p(0xc8, isa->io); in rtrack2_s_frequency()
[all …]
/drivers/ide/
Dali14xx.c93 outb_p(reg, regPort); in inReg()
102 outb_p(reg, regPort); in outReg()
103 outb_p(data, dataPort); in outReg()
138 outb_p(regOn, basePort); in ali14xx_set_pio_mode()
143 outb_p(regOff, basePort); in ali14xx_set_pio_mode()
161 outb_p(regOn, basePort); in findPort()
166 outb_p(regOff, basePort); in findPort()
173 outb_p(regOff, basePort); in findPort()
189 outb_p(regOn, basePort); in initRegisters()
192 outb_p(0x01, regPort); in initRegisters()
[all …]
Dumc8672.c76 outb_p(port, 0x108); in out_umc()
77 outb_p(wert, 0x109); in out_umc()
82 outb_p(port, 0x108); in in_umc()
90 outb_p(0x5A, 0x108); /* enable umc */ in umc_set_speeds()
102 outb_p(0xa5, 0x108); /* disable umc */ in umc_set_speeds()
149 outb_p(0x5A, 0x108); /* enable umc */ in umc8672_probe()
156 outb_p(0xa5, 0x108); /* disable umc */ in umc8672_probe()
/drivers/cpufreq/
Delanfreq.c82 outb_p(0x80, REG_CSCIR); in elanfreq_get_cpu_frequency()
121 outb_p(0x40, REG_CSCIR); /* Disable hyperspeed mode */ in elanfreq_target()
122 outb_p(0x00, REG_CSCDR); in elanfreq_target()
129 outb_p(0x80, REG_CSCIR); in elanfreq_target()
130 outb_p(elan_multiplier[state].val80h, REG_CSCDR); in elanfreq_target()
133 outb_p(0x40, REG_CSCIR); in elanfreq_target()
134 outb_p(elan_multiplier[state].val40h, REG_CSCDR); in elanfreq_target()
/drivers/video/fbdev/
Dhgafb.c146 outb_p(reg, HGA_INDEX_PORT); in write_hga_b()
147 outb_p(val, HGA_VALUE_PORT); in write_hga_b()
152 outb_p(reg, HGA_INDEX_PORT); outb_p(val >> 8, HGA_VALUE_PORT); in write_hga_w()
153 outb_p(reg+1, HGA_INDEX_PORT); outb_p(val & 0xff, HGA_VALUE_PORT); in write_hga_w()
158 outb_p(reg, HGA_INDEX_PORT); in test_hga_b()
184 outb_p(HGA_MODE_VIDEO_EN | HGA_MODE_BLINK_EN, HGA_MODE_PORT); in hga_txt_mode()
185 outb_p(0x00, HGA_GFX_PORT); in hga_txt_mode()
186 outb_p(0x00, HGA_STATUS_PORT); in hga_txt_mode()
215 outb_p(0x00, HGA_STATUS_PORT); in hga_gfx_mode()
216 outb_p(HGA_GFX_MODE_EN, HGA_GFX_PORT); in hga_gfx_mode()
[all …]
/drivers/irqchip/
Dirq-i8259.c242 outb_p(0x11, PIC_MASTER_CMD); /* ICW1: select 8259A-1 init */ in init_8259A()
243 …outb_p(I8259A_IRQ_BASE + 0, PIC_MASTER_IMR); /* ICW2: 8259A-1 IR0 mapped to I8259A_IRQ_BASE + 0x00… in init_8259A()
244 outb_p(1U << PIC_CASCADE_IR, PIC_MASTER_IMR); /* 8259A-1 (the master) has a slave on IR2 */ in init_8259A()
246 outb_p(MASTER_ICW4_DEFAULT | PIC_ICW4_AEOI, PIC_MASTER_IMR); in init_8259A()
248 outb_p(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR); in init_8259A()
250 outb_p(0x11, PIC_SLAVE_CMD); /* ICW1: select 8259A-2 init */ in init_8259A()
251 …outb_p(I8259A_IRQ_BASE + 8, PIC_SLAVE_IMR); /* ICW2: 8259A-2 IR0 mapped to I8259A_IRQ_BASE + 0x08 … in init_8259A()
252 outb_p(PIC_CASCADE_IR, PIC_SLAVE_IMR); /* 8259A-2 is a slave on master's IR2 */ in init_8259A()
253 …outb_p(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR); /* (slave's support for AEOI in flat mode is to be inve… in init_8259A()
/drivers/input/touchscreen/
Dhtcpen.c53 outb_p(TOUCH_INDEX, HTCPEN_PORT_INDEX); in htcpen_interrupt()
58 outb_p(X_INDEX, HTCPEN_PORT_INDEX); in htcpen_interrupt()
61 outb_p(Y_INDEX, HTCPEN_PORT_INDEX); in htcpen_interrupt()
64 outb_p(LSB_XY_INDEX, HTCPEN_PORT_INDEX); in htcpen_interrupt()
91 outb_p(DEVICE_ENABLE, HTCPEN_PORT_INIT); in htcpen_open()
98 outb_p(DEVICE_DISABLE, HTCPEN_PORT_INIT); in htcpen_close()
193 outb_p(DEVICE_DISABLE, HTCPEN_PORT_INIT); in htcpen_isa_suspend()
200 outb_p(DEVICE_ENABLE, HTCPEN_PORT_INIT); in htcpen_isa_resume()

1234