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Searched refs:mcr (Results 1 – 25 of 93) sorted by relevance

12 3 4

/arch/arm/mm/
D	proc-arm940.S	`39 mcr p15, 0, r0, c1, c0, 0 @ disable caches 50 mcr p15, 0, ip, c7, c5, 0 @ flush I cache 51 mcr p15, 0, ip, c7, c6, 0 @ flush D cache 52 mcr p15, 0, ip, c7, c10, 4 @ drain WB 56 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 66 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 76 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 108 mcr p15, 0, ip, c7, c6, 0 @ flush D cache 112 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index 162 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index [all …]`
D	proc-mohawk.S	44 mcr p15, 0, r0, c1, c0, 0 @ disable caches 62 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 63 mcr p15, 0, ip, c7, c10, 4 @ drain WB 64 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 68 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 81 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 82 mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt 92 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 114 mcr p15, 0, ip, c7, c14, 0 @ clean & invalidate all D cache 138 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry [all …]
D	proc-fa526.S	39 mcr p15, 0, r0, c1, c0, 0 @ disable caches 58 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 59 mcr p15, 0, ip, c7, c10, 4 @ drain WB 61 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 67 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 83 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 87 mcr p15, 0, r0, c7, c10, 4 @ drain WB 104 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 106 mcr p15, 0, ip, c7, c14, 0 @ clean and invalidate whole D cache 108 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache [all …]
D	proc-arm946.S	`46 mcr p15, 0, r0, c1, c0, 0 @ disable caches 57 mcr p15, 0, ip, c7, c5, 0 @ flush I cache 58 mcr p15, 0, ip, c7, c6, 0 @ flush D cache 59 mcr p15, 0, ip, c7, c10, 4 @ drain WB 63 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 73 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 83 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 103 mcr p15, 0, ip, c7, c6, 0 @ flush D cache 107 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index 137 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry [all …]`
D	proc-arm1020.S	`69 mcr p15, 0, r0, c1, c0, 0 @ disable caches 85 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 86 mcr p15, 0, ip, c7, c10, 4 @ drain WB 88 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 93 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 103 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 118 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 141 mcr p15, 0, ip, c7, c10, 4 @ drain WB 144 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 145 mcr p15, 0, ip, c7, c10, 4 @ drain WB [all …]`
D	proc-arm926.S	`53 mcr p15, 0, r0, c1, c0, 0 @ disable caches 69 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 70 mcr p15, 0, ip, c7, c10, 4 @ drain WB 72 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 77 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 91 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer 96 mcr p15, 0, r2, c1, c0, 0 @ Disable I cache 97 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 98 mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable 109 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache [all …]`
D	proc-arm925.S	84 mcr p15, 0, r0, c1, c0, 0 @ disable caches 109 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 110 mcr p15, 0, ip, c7, c10, 4 @ drain WB 112 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 117 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 129 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer 131 mcr p15, 0, r2, c1, c0, 0 @ Disable I cache 132 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 133 mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable 143 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache [all …]
D	proc-arm920.S	61 mcr p15, 0, r0, c1, c0, 0 @ disable caches 77 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 78 mcr p15, 0, ip, c7, c10, 4 @ drain WB 80 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 85 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 95 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 108 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 132 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 158 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 193 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry [all …]
D	proc-sa1100.S	41 mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching 42 mcr p15, 0, r0, c9, c0, 5 @ Allow read-buffer operations from userland 53 mcr p15, 0, ip, c15, c2, 2 @ Disable clock switching 57 mcr p15, 0, r0, c1, c0, 0 @ disable caches 73 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 74 mcr p15, 0, ip, c7, c10, 4 @ drain WB 76 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 81 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 108 mcr p15, 0, r0, c15, c2, 2 @ disable clock switching 110 mcr p15, 0, r0, c15, c8, 2 @ wait for interrupt [all …]
D	proc-v6.S	`42 mcr p15, 0, r0, c1, c0, 0 @ disable caches 59 mcr p15, 0, r1, c1, c0, 0 @ disable MMU 61 mcr p15, 0, r1, c7, c5, 4 @ ISB 75 mcr p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode 76 mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt 80 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 102 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB 103 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer 104 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 111 mcr p15, 0, r1, c13, c0, 1 @ set context ID [all …]`
D	proc-arm922.S	63 mcr p15, 0, r0, c1, c0, 0 @ disable caches 79 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 80 mcr p15, 0, ip, c7, c10, 4 @ drain WB 82 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 87 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 97 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 110 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 134 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 160 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 195 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry [all …]
D	cache-v6.S	40 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 41 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 42 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 43 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 49 mcr p15, 0, r0, c7, c5, 0 @ invalidate I-cache 64 mcr p15, 0, r0, c7, c14, 0 @ D cache clean+invalidate 66 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate 71 mcr p15, 0, r0, c7, c15, 0 @ Cache clean+invalidate 134 USER( mcr p15, 0, r0, c7, c10, 1 ) @ clean D line 141 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer [all …]
D	proc-arm1020e.S	69 mcr p15, 0, r0, c1, c0, 0 @ disable caches 85 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 86 mcr p15, 0, ip, c7, c10, 4 @ drain WB 88 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 93 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 103 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 118 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 141 mcr p15, 0, ip, c7, c10, 4 @ drain WB 144 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 174 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry [all …]
D	proc-feroceon.S	`68 mcr p15, 1, r0, c15, c9, 0 @ clean L2 69 mcr p15, 0, r0, c7, c10, 4 @ drain WB 75 mcr p15, 0, r0, c1, c0, 0 @ disable caches 91 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 92 mcr p15, 0, ip, c7, c10, 4 @ drain WB 94 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 99 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 112 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer 113 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 123 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache [all …]`
D	proc-sa110.S	37 mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching 45 mcr p15, 0, r0, c15, c2, 2 @ Disable clock switching 49 mcr p15, 0, r0, c1, c0, 0 @ disable caches 65 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 66 mcr p15, 0, ip, c7, c10, 4 @ drain WB 68 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 73 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 92 mcr p15, 0, ip, c15, c2, 2 @ disable clock switching 98 mcr p15, 0, r0, c15, c8, 2 @ Wait for interrupt, cache aligned 102 mcr p15, 0, r0, c15, c1, 2 @ enable clock switching [all …]
D	proc-xscale.S	91 1: mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 93 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 95 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 97 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 118 mcr p15, 0, r1, c1, c0, 1 128 mcr p15, 0, r0, c1, c0, 0 @ disable caches 147 mcr p15, 0, r1, c10, c4, 1 @ unlock I-TLB 148 mcr p15, 0, r1, c8, c5, 0 @ invalidate I-TLB 154 mcr p15, 0, r1, c1, c0, 0 @ ctrl register 156 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches & BTB [all …]
D	proc-xsc3.S	68 1: mcr p15, 0, \rd, c7, c14, 2 @ clean/invalidate L1 D line 92 mcr p15, 0, r0, c1, c0, 0 @ disable caches 112 mcr p15, 0, r1, c1, c0, 0 @ ctrl register 113 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB 115 mcr p15, 0, r1, c1, c0, 0 @ ctrl register 118 mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs 137 mcr p14, 0, r0, c7, c0, 0 @ go to idle 149 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 197 mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line 224 1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line [all …]
D	proc-arm1022.S	69 mcr p15, 0, r0, c1, c0, 0 @ disable caches 85 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 86 mcr p15, 0, ip, c7, c10, 4 @ drain WB 88 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 93 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 103 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 118 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 143 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 173 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 213 mcr p15, 0, r0, c7, c10, 1 @ clean D entry [all …]
D	proc-arm1026.S	69 mcr p15, 0, r0, c1, c0, 0 @ disable caches 85 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 86 mcr p15, 0, ip, c7, c10, 4 @ drain WB 88 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 93 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 103 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 118 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 168 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 207 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 210 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry [all …]
D	proc-arm740.S	`40 mcr p15, 0, r0, c1, c0, 0 @ disable caches 51 mcr p15, 0, ip, c7, c0, 0 @ invalidate cache 54 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 62 mcr p15, 0, r0, c7, c0, 0 @ invalidate caches 64 mcr p15, 0, r0, c6, c3 @ disable area 3~7 65 mcr p15, 0, r0, c6, c4 66 mcr p15, 0, r0, c6, c5 67 mcr p15, 0, r0, c6, c6 68 mcr p15, 0, r0, c6, c7 71 mcr p15, 0, r0, c6, c0 @ set area 0, default [all …]`
D	cache-fa.S	45 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 66 mcr p15, 0, ip, c7, c14, 0 @ clean/invalidate D cache 92 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 127 1: mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 128 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 133 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB 134 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 135 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush 149 1: mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line 154 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache [all …]
D	tlb-v6.S	37 mcr p15, 0, ip, c7, c10, 4 @ drain write buffer 46 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA (was 1) 50 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA (was 1) 55 mcr p15, 0, ip, c7, c10, 4 @ data synchronization barrier 68 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer 75 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA 76 mcr p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA 78 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA 83 mcr p15, 0, r2, c7, c10, 4 @ data synchronization barrier 84 mcr p15, 0, r2, c7, c5, 4 @ prefetch flush (isb)
D	tlb-fa.S	`40 mcr p15, 0, r3, c7, c10, 4 @ drain WB 43 1: mcr p15, 0, r0, c8, c7, 1 @ invalidate UTLB entry 47 mcr p15, 0, r3, c7, c10, 4 @ data write barrier 53 mcr p15, 0, r3, c7, c10, 4 @ drain WB 56 1: mcr p15, 0, r0, c8, c7, 1 @ invalidate UTLB entry 60 mcr p15, 0, r3, c7, c10, 4 @ data write barrier 61 mcr p15, 0, r3, c7, c5, 4 @ prefetch flush (isb)`
D	cache-v4wb.S	59 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 78 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 95 mcr p15, 0, ip, c7, c10, 4 @ drain write buffer 117 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 118 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 164 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 165 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 170 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 171 mcr p15, 0, r0, c7, c10, 4 @ drain WB 192 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry [all …]
/arch/sh/drivers/pci/
D	fixups-landisk.c	`41 unsigned long bcr1, mcr; in pci_fixup_pcic() local 47 mcr = __raw_readl(SH7751_MCR); in pci_fixup_pcic() 48 mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF; in pci_fixup_pcic() 49 pci_write_reg(chan, mcr, SH4_PCIMCR); in pci_fixup_pcic()`

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