Searched refs:TRANSCODER_A (Results 1 – 12 of 12) sorted by relevance
/drivers/gpu/drm/i915/ |
D | i915_pci.c | 41 [TRANSCODER_A] = PIPE_A_OFFSET, \ 44 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 49 [TRANSCODER_A] = PIPE_A_OFFSET, \ 53 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 59 [TRANSCODER_A] = PIPE_A_OFFSET, \ 64 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 71 [TRANSCODER_A] = PIPE_A_OFFSET, \ 77 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ 85 [TRANSCODER_A] = PIPE_A_OFFSET, \ 90 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ [all …]
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D | intel_device_info.c | 341 info->cpu_transcoder_mask &= ~BIT(TRANSCODER_A); in intel_device_info_runtime_init()
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D | i915_irq.c | 3121 u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | in gen11_display_irq_reset() 3754 u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | in gen8_de_irq_postinstall()
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D | i915_reg.h | 258 INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_A] + (reg) + \ 4565 0 : ((trans) - TRANSCODER_A + 1) * 8) 8237 [TRANSCODER_A] = _CHICKEN_TRANS_A, \
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/drivers/gpu/drm/i915/gvt/ |
D | display.c | 194 for (trans = TRANSCODER_A; trans <= TRANSCODER_EDP; trans++) { in emulate_monitor_status_change() 199 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &= in emulate_monitor_status_change() 256 vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = 63 << TU_SIZE_SHIFT; in emulate_monitor_status_change() 257 vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) |= 0x5b425e; in emulate_monitor_status_change() 258 vgpu_vreg_t(vgpu, PIPE_DATA_N1(TRANSCODER_A)) = 0x800000; in emulate_monitor_status_change() 259 vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e; in emulate_monitor_status_change() 260 vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000; in emulate_monitor_status_change() 311 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |= in emulate_monitor_status_change() 341 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |= in emulate_monitor_status_change() 390 vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = 63 << TU_SIZE_SHIFT; in emulate_monitor_status_change() [all …]
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D | handlers.c | 652 port = (vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) & in vgpu_update_refresh_rate() 668 link_m = vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)); in vgpu_update_refresh_rate() 669 link_n = vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)); in vgpu_update_refresh_rate() 672 htotal = (vgpu_vreg_t(vgpu, HTOTAL(TRANSCODER_A)) >> TRANS_HTOTAL_SHIFT); in vgpu_update_refresh_rate() 673 vtotal = (vgpu_vreg_t(vgpu, VTOTAL(TRANSCODER_A)) >> TRANS_VTOTAL_SHIFT); in vgpu_update_refresh_rate() 2413 MMIO_D(HTOTAL(TRANSCODER_A), D_ALL); in init_generic_mmio_info() 2414 MMIO_D(HBLANK(TRANSCODER_A), D_ALL); in init_generic_mmio_info() 2415 MMIO_D(HSYNC(TRANSCODER_A), D_ALL); in init_generic_mmio_info() 2416 MMIO_D(VTOTAL(TRANSCODER_A), D_ALL); in init_generic_mmio_info() 2417 MMIO_D(VBLANK(TRANSCODER_A), D_ALL); in init_generic_mmio_info() [all …]
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/drivers/gpu/drm/i915/display/ |
D | intel_display.h | 106 TRANSCODER_A = PIPE_A, enumerator 127 case TRANSCODER_A: in transcoder_name()
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D | intel_dp_hdcp.c | 26 case TRANSCODER_A: in transcoder_to_stream_enc_status()
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D | intel_hdcp.c | 340 case TRANSCODER_A: in intel_hdcp_get_repeater_ctl() 2155 case TRANSCODER_A ... TRANSCODER_D: in intel_get_mei_fw_tc()
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D | intel_ddi.c | 3028 [PORT_B] = TRANSCODER_A, in gen9_chicken_trans_reg_by_port() 3031 [PORT_E] = TRANSCODER_A, in gen9_chicken_trans_reg_by_port() 3470 u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | in bdw_get_trans_port_sync_config()
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D | intel_psr.c | 626 return trans == TRANSCODER_A; in transcoder_has_psr2()
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D | intel_dp.c | 922 if (DISPLAY_VER(dev_priv) == 11 && pipe_config->cpu_transcoder != TRANSCODER_A) in intel_dp_source_supports_fec()
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