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Searched refs:cr1 (Results 1 – 20 of 20) sorted by relevance

/drivers/spi/
Dspi-sh.c78 unsigned long cr1; member
188 ss->cr1 &= ~SPI_SH_TBE; in spi_sh_send()
191 ss->cr1 & SPI_SH_TBE, in spi_sh_send()
193 if (ret == 0 && !(ss->cr1 & SPI_SH_TBE)) { in spi_sh_send()
204 ss->cr1 &= ~SPI_SH_TBE; in spi_sh_send()
207 ss->cr1 & SPI_SH_TBE, in spi_sh_send()
209 if (ret == 0 && (ss->cr1 & SPI_SH_TBE)) { in spi_sh_send()
240 ss->cr1 &= ~SPI_SH_RBF; in spi_sh_receive()
243 ss->cr1 & SPI_SH_RBF, in spi_sh_receive()
394 unsigned long cr1; in spi_sh_irq() local
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Dspi-pxa2xx.c970 u32 cr1; in pxa2xx_spi_transfer_one() local
1056 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1; in pxa2xx_spi_transfer_one()
1065 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1; in pxa2xx_spi_transfer_one()
1108 pxa2xx_spi_update(drv_data, SSCR1, change_mask, cr1); in pxa2xx_spi_transfer_one()
1142 pxa2xx_spi_write(drv_data, SSCR1, cr1); in pxa2xx_spi_transfer_one()
1319 chip->cr1 = 0; in setup()
1331 chip->cr1 = SSCR1_LBM; in setup()
1334 chip->cr1 |= SSCR1_SCFR; in setup()
1335 chip->cr1 |= SSCR1_SCLKDIR; in setup()
1336 chip->cr1 |= SSCR1_SFRMDIR; in setup()
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Dspi-pl022.c421 u16 cr1; member
560 writew(chip->cr1, SSP_CR1(pl022->virtbase)); in restore_state()
1963 chip->cr1 = 0; in pl022_setup()
1991 SSP_WRITE_BITS(chip->cr1, chip_info->clkdelay, in pl022_setup()
2001 SSP_WRITE_BITS(chip->cr1, chip_info->wait_state, in pl022_setup()
2014 SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_RENDN_ST, 4); in pl022_setup()
2015 SSP_WRITE_BITS(chip->cr1, etx, SSP_CR1_MASK_TENDN_ST, 5); in pl022_setup()
2016 SSP_WRITE_BITS(chip->cr1, chip_info->rx_lev_trig, in pl022_setup()
2018 SSP_WRITE_BITS(chip->cr1, chip_info->tx_lev_trig, in pl022_setup()
2047 SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_LBM, 0); in pl022_setup()
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Dspi-rockchip.c528 u32 cr1; in rockchip_spi_config() local
552 cr1 = xfer->len - 1; in rockchip_spi_config()
556 cr1 = xfer->len - 1; in rockchip_spi_config()
560 cr1 = xfer->len / 2 - 1; in rockchip_spi_config()
580 writel_relaxed(cr1, rs->regs + ROCKCHIP_SPI_CTRLR1); in rockchip_spi_config()
Dspi-pxa2xx.h61 u32 cr1; member
Dspi-stm32.c689 u32 cr1; in stm32h7_spi_disable() local
695 cr1 = readl_relaxed(spi->base + STM32H7_SPI_CR1); in stm32h7_spi_disable()
697 if (!(cr1 & STM32H7_SPI_CR1_SPE)) { in stm32h7_spi_disable()
/drivers/counter/
Dstm32-timer-cnt.c25 u32 cr1; member
104 u32 cr1, sms; in stm32_count_function_write() local
124 regmap_read(priv->regmap, TIM_CR1, &cr1); in stm32_count_function_write()
134 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, cr1); in stm32_count_function_write()
144 u32 cr1; in stm32_count_direction_read() local
146 regmap_read(priv->regmap, TIM_CR1, &cr1); in stm32_count_direction_read()
147 *direction = (cr1 & TIM_CR1_DIR) ? COUNTER_COUNT_DIRECTION_BACKWARD : in stm32_count_direction_read()
185 u32 cr1; in stm32_count_enable_read() local
187 regmap_read(priv->regmap, TIM_CR1, &cr1); in stm32_count_enable_read()
189 *enable = cr1 & TIM_CR1_CEN; in stm32_count_enable_read()
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/drivers/tty/serial/
Dstm32-usart.c111 static void stm32_usart_config_reg_rs485(u32 *cr1, u32 *cr3, u32 delay_ADE, in stm32_usart_config_reg_rs485() argument
119 over8 = *cr1 & USART_CR1_OVER8; in stm32_usart_config_reg_rs485()
121 *cr1 &= ~(USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK); in stm32_usart_config_reg_rs485()
133 *cr1 |= rs485_deat_dedt; in stm32_usart_config_reg_rs485()
145 *cr1 |= rs485_deat_dedt; in stm32_usart_config_reg_rs485()
154 u32 usartdiv, baud, cr1, cr3; in stm32_usart_config_rs485() local
157 stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); in stm32_usart_config_rs485()
164 cr1 = readl_relaxed(port->membase + ofs->cr1); in stm32_usart_config_rs485()
168 over8 = cr1 & USART_CR1_OVER8; in stm32_usart_config_rs485()
175 stm32_usart_config_reg_rs485(&cr1, &cr3, in stm32_usart_config_rs485()
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Dfsl_linflexuart.c329 unsigned long cr, ier, cr1; in linflex_setup_watermark() local
343 cr1 = LINFLEXD_LINCR1_BF | LINFLEXD_LINCR1_MME in linflex_setup_watermark()
345 writel(cr1, sport->membase + LINCR1); in linflex_setup_watermark()
369 cr1 &= ~(LINFLEXD_LINCR1_INIT); in linflex_setup_watermark()
371 writel(cr1, sport->membase + LINCR1); in linflex_setup_watermark()
419 unsigned long cr, old_cr, cr1; in linflex_set_termios() local
426 cr1 = readl(port->membase + LINCR1); in linflex_set_termios()
427 cr1 |= LINFLEXD_LINCR1_INIT; in linflex_set_termios()
428 writel(cr1, port->membase + LINCR1); in linflex_set_termios()
519 cr1 &= ~(LINFLEXD_LINCR1_INIT); in linflex_set_termios()
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Dstm32-usart.h12 u8 cr1; member
48 .cr1 = 0x0c,
65 .cr1 = 0x00,
87 .cr1 = 0x00,
Dfsl_lpuart.c1874 unsigned char cr1, old_cr1, old_cr2, cr3, cr4, bdh, modem; in lpuart_set_termios() local
1879 cr1 = old_cr1 = readb(sport->port.membase + UARTCR1); in lpuart_set_termios()
1902 cr1 = old_cr1 & ~UARTCR1_M; in lpuart_set_termios()
1909 cr1 |= UARTCR1_M; in lpuart_set_termios()
1932 cr1 &= ~UARTCR1_PE; in lpuart_set_termios()
1938 cr1 |= UARTCR1_PE; in lpuart_set_termios()
1940 cr1 |= UARTCR1_M; in lpuart_set_termios()
1942 cr1 |= UARTCR1_PT; in lpuart_set_termios()
1944 cr1 &= ~UARTCR1_PT; in lpuart_set_termios()
1947 cr1 &= ~UARTCR1_PE; in lpuart_set_termios()
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/drivers/i2c/busses/
Di2c-stm32f4.c489 u32 cr1; in stm32f4_i2c_handle_rx_addr() local
506 cr1 = readl_relaxed(i2c_dev->base + STM32F4_I2C_CR1); in stm32f4_i2c_handle_rx_addr()
507 cr1 &= ~(STM32F4_I2C_CR1_ACK | STM32F4_I2C_CR1_POS); in stm32f4_i2c_handle_rx_addr()
508 writel_relaxed(cr1, i2c_dev->base + STM32F4_I2C_CR1); in stm32f4_i2c_handle_rx_addr()
513 cr1 |= STM32F4_I2C_CR1_STOP; in stm32f4_i2c_handle_rx_addr()
515 cr1 |= STM32F4_I2C_CR1_START; in stm32f4_i2c_handle_rx_addr()
516 writel_relaxed(cr1, i2c_dev->base + STM32F4_I2C_CR1); in stm32f4_i2c_handle_rx_addr()
526 cr1 = readl_relaxed(i2c_dev->base + STM32F4_I2C_CR1); in stm32f4_i2c_handle_rx_addr()
527 cr1 &= ~STM32F4_I2C_CR1_ACK; in stm32f4_i2c_handle_rx_addr()
528 cr1 |= STM32F4_I2C_CR1_POS; in stm32f4_i2c_handle_rx_addr()
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Di2c-stm32f7.c193 u32 cr1; member
873 u32 cr1, cr2; in stm32f7_i2c_xfer_msg() local
884 cr1 = readl_relaxed(base + STM32F7_I2C_CR1); in stm32f7_i2c_xfer_msg()
913 cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE | in stm32f7_i2c_xfer_msg()
917 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE | in stm32f7_i2c_xfer_msg()
936 cr1 |= STM32F7_I2C_CR1_RXIE; in stm32f7_i2c_xfer_msg()
938 cr1 |= STM32F7_I2C_CR1_TXIE; in stm32f7_i2c_xfer_msg()
941 cr1 |= STM32F7_I2C_CR1_RXDMAEN; in stm32f7_i2c_xfer_msg()
943 cr1 |= STM32F7_I2C_CR1_TXDMAEN; in stm32f7_i2c_xfer_msg()
952 writel_relaxed(cr1, base + STM32F7_I2C_CR1); in stm32f7_i2c_xfer_msg()
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/drivers/staging/media/imx/
Dimx7-media-csi.c241 u32 cr1 = imx7_csi_reg_read(csi, CSI_CSICR1); in imx7_csi_hw_enable_irq() local
243 cr1 |= BIT_RFF_OR_INT; in imx7_csi_hw_enable_irq()
244 cr1 |= BIT_FB1_DMA_DONE_INTEN; in imx7_csi_hw_enable_irq()
245 cr1 |= BIT_FB2_DMA_DONE_INTEN; in imx7_csi_hw_enable_irq()
247 imx7_csi_reg_write(csi, cr1, CSI_CSICR1); in imx7_csi_hw_enable_irq()
252 u32 cr1 = imx7_csi_reg_read(csi, CSI_CSICR1); in imx7_csi_hw_disable_irq() local
254 cr1 &= ~BIT_RFF_OR_INT; in imx7_csi_hw_disable_irq()
255 cr1 &= ~BIT_FB1_DMA_DONE_INTEN; in imx7_csi_hw_disable_irq()
256 cr1 &= ~BIT_FB2_DMA_DONE_INTEN; in imx7_csi_hw_disable_irq()
258 imx7_csi_reg_write(csi, cr1, CSI_CSICR1); in imx7_csi_hw_disable_irq()
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/drivers/input/touchscreen/
Dmc13783_ts.c71 int cr0, cr1; in mc13783_ts_report_sample() local
84 cr1 = (priv->sample[3] >> 12) & 0xfff; in mc13783_ts_report_sample()
88 x0, x1, x2, y0, y1, y2, cr0, cr1); in mc13783_ts_report_sample()
93 cr0 = (cr0 + cr1) / 2; in mc13783_ts_report_sample()
/drivers/iio/trigger/
Dstm32-timer-trigger.c79 u32 cr1; member
241 u32 psc, arr, cr1; in stm32_tt_read_frequency() local
244 regmap_read(priv->regmap, TIM_CR1, &cr1); in stm32_tt_read_frequency()
248 if (cr1 & TIM_CR1_CEN) { in stm32_tt_read_frequency()
837 regmap_read(priv->regmap, TIM_CR1, &priv->bak.cr1); in stm32_timer_trigger_suspend()
872 regmap_write(priv->regmap, TIM_CR1, priv->bak.cr1); in stm32_timer_trigger_resume()
/drivers/iio/adc/
Dstm32-dfsdm-adc.c506 u32 cr1; in stm32_dfsdm_filter_configure() local
562 cr1 = DFSDM_CR1_RCH(chan->channel); in stm32_dfsdm_filter_configure()
566 cr1 |= DFSDM_CR1_RCONT(1); in stm32_dfsdm_filter_configure()
568 cr1 |= DFSDM_CR1_RSYNC(fl->sync_mode); in stm32_dfsdm_filter_configure()
581 cr1 = DFSDM_CR1_JSCAN((adc->nconv > 1) ? 1 : 0); in stm32_dfsdm_filter_configure()
591 cr1 |= DFSDM_CR1_JSYNC(fl->sync_mode); in stm32_dfsdm_filter_configure()
595 cr1); in stm32_dfsdm_filter_configure()
/drivers/mtd/devices/
Dst_spi_fsm.c1393 uint8_t sr1, cr1, dyb; in stfsm_s25fl_config() local
1443 stfsm_read_status(fsm, SPINOR_OP_RDCR, &cr1, 1); in stfsm_s25fl_config()
1446 if (!(cr1 & STFSM_S25FL_CONFIG_QE)) { in stfsm_s25fl_config()
1448 cr1 |= STFSM_S25FL_CONFIG_QE; in stfsm_s25fl_config()
1453 if (cr1 & STFSM_S25FL_CONFIG_QE) { in stfsm_s25fl_config()
1455 cr1 &= ~STFSM_S25FL_CONFIG_QE; in stfsm_s25fl_config()
1462 sta_wr = ((uint16_t)cr1 << 8) | sr1; in stfsm_s25fl_config()
/drivers/gpu/drm/mcde/
Dmcde_display.c635 u32 cr0, cr1; in mcde_configure_fifo() local
641 cr1 = MCDE_CRA1; in mcde_configure_fifo()
646 cr1 = MCDE_CRB1; in mcde_configure_fifo()
702 val = readl(mcde->regs + cr1); in mcde_configure_fifo()
743 writel(val, mcde->regs + cr1); in mcde_configure_fifo()
/drivers/parport/
Dparport_pc.c950 int cr1, cr4, cra, cr23, cr26, cr27; in show_parconfig_smsc37c669() local
962 cr1 = inb(io + 1); in show_parconfig_smsc37c669()
977 cr1, cr4, cra, cr23, cr26, cr27); in show_parconfig_smsc37c669()
989 (cr1 & 4) ? "yes" : "no"); in show_parconfig_smsc37c669()
991 (cr1 & 0x08) ? "Standard mode only (SPP)" in show_parconfig_smsc37c669()