| /drivers/media/i2c/adv748x/ |
| D | adv748x-core.c | 367 tx->active_lanes = min(tx->num_lanes, 2U); in adv748x_link_setup()
380 tx->active_lanes = tx->num_lanes; in adv748x_link_setup()
613 unsigned int num_lanes; in adv748x_parse_csi2_lanes() local
623 num_lanes = vep.bus.mipi_csi2.num_data_lanes; in adv748x_parse_csi2_lanes()
626 if (num_lanes != 1 && num_lanes != 2 && num_lanes != 4) { in adv748x_parse_csi2_lanes()
628 num_lanes); in adv748x_parse_csi2_lanes()
632 state->txa.num_lanes = num_lanes; in adv748x_parse_csi2_lanes()
633 state->txa.active_lanes = num_lanes; in adv748x_parse_csi2_lanes()
634 adv_dbg(state, "TXA: using %u lanes\n", state->txa.num_lanes); in adv748x_parse_csi2_lanes()
638 if (num_lanes != 1) { in adv748x_parse_csi2_lanes()
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| /drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| D | pppcielanes.c | 56 uint8_t encode_pcie_lane_width(uint32_t num_lanes) in encode_pcie_lane_width() argument
58 return pp_r600_encode_lanes[num_lanes]; in encode_pcie_lane_width()
61 uint8_t decode_pcie_lane_width(uint32_t num_lanes) in decode_pcie_lane_width() argument
63 return pp_r600_decoded_lanes[num_lanes]; in decode_pcie_lane_width()
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| D | pppcielanes.h | 27 extern uint8_t encode_pcie_lane_width(uint32_t num_lanes);
28 extern uint8_t decode_pcie_lane_width(uint32_t num_lanes);
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| /drivers/phy/ti/ |
| D | phy-j721e-wiz.c | 284 u32 num_lanes; member
314 u32 num_lanes = wiz->num_lanes; in wiz_p_mac_div_sel() local
318 for (i = 0; i < num_lanes; i++) { in wiz_p_mac_div_sel()
335 u32 num_lanes = wiz->num_lanes; in wiz_mode_select() local
340 for (i = 0; i < num_lanes; i++) { in wiz_mode_select()
358 u32 num_lanes = wiz->num_lanes; in wiz_init_raw_interface() local
362 for (i = 0; i < num_lanes; i++) { in wiz_init_raw_interface()
410 int num_lanes = wiz->num_lanes; in wiz_regfield_init() local
486 for (i = 0; i < num_lanes; i++) { in wiz_regfield_init()
1106 u32 reg, num_lanes = 1, phy_type = PHY_NONE; in wiz_get_lane_phy_types() local
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| /drivers/pci/controller/dwc/ |
| D | pci-keystone.c | 123 int num_lanes; member
948 int num_lanes = ks_pcie->num_lanes; in ks_pcie_disable_phy() local
950 while (num_lanes--) { in ks_pcie_disable_phy()
951 phy_power_off(ks_pcie->phy[num_lanes]); in ks_pcie_disable_phy()
952 phy_exit(ks_pcie->phy[num_lanes]); in ks_pcie_disable_phy()
960 int num_lanes = ks_pcie->num_lanes; in ks_pcie_enable_phy() local
962 for (i = 0; i < num_lanes; i++) { in ks_pcie_enable_phy()
1101 u32 num_lanes; in ks_pcie_probe() local
1158 ret = of_property_read_u32(np, "num-lanes", &num_lanes); in ks_pcie_probe()
1160 num_lanes = 1; in ks_pcie_probe()
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| D | pcie-designware.c | 758 of_property_read_u32(np, "num-lanes", &pci->num_lanes); in dw_pcie_setup()
759 if (!pci->num_lanes) { in dw_pcie_setup()
767 switch (pci->num_lanes) { in dw_pcie_setup()
781 dev_err(pci->dev, "num-lanes %u: invalid value\n", pci->num_lanes); in dw_pcie_setup()
789 switch (pci->num_lanes) { in dw_pcie_setup()
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| /drivers/gpu/drm/bridge/cadence/ |
| D | cdns-mhdp8546-core.c | 613 values[1] = link->num_lanes; in cdns_mhdp_link_configure()
878 CDNS_DP_LANE_EN_LANES(mhdp->link.num_lanes)); in cdns_mhdp_link_training_init()
882 phy_cfg.dp.lanes = mhdp->link.num_lanes; in cdns_mhdp_link_training_init()
923 for (i = 0; i < mhdp->link.num_lanes; i++) { in cdns_mhdp_get_adjust_train()
988 for (i = 0; i < mhdp->link.num_lanes; i++) { in cdns_mhdp_adjust_requested_eq()
1011 for (i = 0; i < mhdp->link.num_lanes; i++) { in cdns_mhdp_print_lt_status()
1021 mhdp->link.num_lanes, mhdp->link.rate / 100, in cdns_mhdp_print_lt_status()
1054 phy_cfg.dp.lanes = mhdp->link.num_lanes; in cdns_mhdp_link_training_channel_eq()
1066 cdns_mhdp_adjust_lt(mhdp, mhdp->link.num_lanes, in cdns_mhdp_link_training_channel_eq()
1069 r = drm_dp_clock_recovery_ok(link_status, mhdp->link.num_lanes); in cdns_mhdp_link_training_channel_eq()
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| /drivers/gpu/drm/bridge/adv7511/ |
| D | adv7533.c | 190 u32 num_lanes; in adv7533_parse_dt() local
192 of_property_read_u32(np, "adi,dsi-lanes", &num_lanes); in adv7533_parse_dt()
194 if (num_lanes < 1 || num_lanes > 4) in adv7533_parse_dt()
197 adv->num_dsi_lanes = num_lanes; in adv7533_parse_dt()
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| /drivers/nvdimm/ |
| D | region.c | 19 if (nd_region->num_lanes > num_online_cpus() in nd_region_probe()
20 && nd_region->num_lanes < num_possible_cpus() in nd_region_probe()
23 num_online_cpus(), nd_region->num_lanes, in nd_region_probe()
26 nd_region->num_lanes); in nd_region_probe()
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| D | region_devs.c | 971 if (nd_region->num_lanes < nr_cpu_ids) { in nd_region_acquire_lane()
974 lane = cpu % nd_region->num_lanes; in nd_region_acquire_lane()
988 if (nd_region->num_lanes < nr_cpu_ids) { in nd_region_release_lane()
1126 nd_region->num_lanes = ndr_desc->num_lanes; in nd_region_create()
1163 ndr_desc->num_lanes = ND_MAX_LANES; in nvdimm_pmem_region_create()
1174 ndr_desc->num_lanes = min(ndr_desc->num_lanes, ND_MAX_LANES); in nvdimm_blk_region_create()
1183 ndr_desc->num_lanes = ND_MAX_LANES; in nvdimm_volatile_region_create()
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| /drivers/media/platform/cadence/ |
| D | cdns-csi2rx.c | 74 u8 num_lanes; member
117 reg = csi2rx->num_lanes << 8; in csi2rx_start()
118 for (i = 0; i < csi2rx->num_lanes; i++) { in csi2rx_start()
129 for (i = csi2rx->num_lanes; i < csi2rx->max_lanes; i++) { in csi2rx_start()
396 csi2rx->num_lanes = v4l2_ep.bus.mipi_csi2.num_data_lanes; in csi2rx_parse_dt()
397 if (csi2rx->num_lanes > csi2rx->max_lanes) { in csi2rx_parse_dt()
399 csi2rx->num_lanes); in csi2rx_parse_dt()
470 csi2rx->num_lanes, csi2rx->max_lanes, csi2rx->max_streams, in csi2rx_probe()
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| D | cdns-csi2tx.c | 115 unsigned int num_lanes; member
251 for (i = 0; i < csi2tx->num_lanes; i++) in csi2tx_dphy_init_finish()
273 for (i = 0; i < csi2tx->num_lanes; i++) in csi2tx_dphy_setup()
521 csi2tx->num_lanes = v4l2_ep.bus.mipi_csi2.num_data_lanes; in csi2tx_check_lanes()
522 if (csi2tx->num_lanes > csi2tx->max_lanes) { in csi2tx_check_lanes()
529 for (i = 0; i < csi2tx->num_lanes; i++) { in csi2tx_check_lanes()
629 csi2tx->num_lanes, csi2tx->max_lanes, csi2tx->max_streams, in csi2tx_probe()
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| /drivers/gpu/drm/msm/dp/ |
| D | dp_panel.c | 74 link_info->num_lanes = dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; in dp_panel_read_dpcd()
76 if (link_info->num_lanes > dp_panel->max_dp_lanes) in dp_panel_read_dpcd()
77 link_info->num_lanes = dp_panel->max_dp_lanes; in dp_panel_read_dpcd()
85 DRM_DEBUG_DP("lane_count=%d\n", link_info->num_lanes); in dp_panel_read_dpcd()
121 data_rate_khz = link_info->num_lanes * link_info->rate * 8; in dp_panel_get_supported_bpp()
176 !is_lane_count_valid(dp_panel->link_info.num_lanes) || in dp_panel_read_sink_caps()
179 dp_panel->link_info.num_lanes); in dp_panel_read_sink_caps()
216 !is_lane_count_valid(dp_panel->link_info.num_lanes) in dp_panel_read_sink_caps()
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| D | dp_ctrl.c | 91 values[1] = link->num_lanes; in dp_aux_link_configure()
142 config |= ((ctrl->link->link_params.num_lanes - 1) in dp_ctrl_config_ctrl()
947 in.nlanes = ctrl->link->link_params.num_lanes; in dp_ctrl_calc_tu_parameters()
1029 lane_cnt = ctrl->link->link_params.num_lanes; in dp_ctrl_update_vx_px()
1106 ctrl->link->link_params.num_lanes)) { in dp_ctrl_link_train_1()
1162 if (ctrl->link->link_params.num_lanes == 1) in dp_ctrl_link_lane_down_shift()
1165 ctrl->link->link_params.num_lanes /= 2; in dp_ctrl_link_lane_down_shift()
1211 ctrl->link->link_params.num_lanes)) { in dp_ctrl_link_train_2()
1236 link_info.num_lanes = ctrl->link->link_params.num_lanes; in dp_ctrl_link_train()
1316 opts_dp->lanes = ctrl->link->link_params.num_lanes; in dp_ctrl_enable_mainlink_clocks()
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| D | dp_link.c | 783 link->dp_link.link_params.num_lanes = link->request.test_lane_count; in dp_link_process_link_training_request()
913 link->dp_link.link_params.num_lanes); in dp_link_process_phy_test_pattern_request()
919 link->dp_link.link_params.num_lanes = link->request.test_lane_count; in dp_link_process_phy_test_pattern_request()
947 link->dp_link.link_params.num_lanes); in dp_link_process_link_status_update()
950 link->dp_link.link_params.num_lanes); in dp_link_process_link_status_update()
1102 for (i = 0; i < dp_link->link_params.num_lanes; i++) { in dp_link_adjust_levels()
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| /drivers/pci/controller/cadence/ |
| D | pci-j721e.c | 57 u32 num_lanes; member
209 u32 lanes = pcie->num_lanes; in j721e_pcie_set_lane_count()
365 u32 num_lanes; in j721e_pcie_probe() local
394 ret = of_property_read_u32(node, "num-lanes", &num_lanes); in j721e_pcie_probe()
395 if (ret || num_lanes > MAX_LANES) in j721e_pcie_probe()
396 num_lanes = 1; in j721e_pcie_probe()
397 pcie->num_lanes = num_lanes; in j721e_pcie_probe()
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| /drivers/staging/media/imx/ |
| D | imx6-mipi-csi2.c | 306 unsigned int num_lanes = UINT_MAX; in csi2_get_active_lanes() local
331 num_lanes = 1; in csi2_get_active_lanes()
334 num_lanes = 2; in csi2_get_active_lanes()
337 num_lanes = 3; in csi2_get_active_lanes()
340 num_lanes = 4; in csi2_get_active_lanes()
343 num_lanes = csi2->data_lanes; in csi2_get_active_lanes()
347 if (num_lanes > csi2->data_lanes) { in csi2_get_active_lanes()
350 num_lanes); in csi2_get_active_lanes()
354 *lanes = num_lanes; in csi2_get_active_lanes()
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| /drivers/phy/cadence/ |
| D | phy-cadence-torrent.c | 305 u32 num_lanes; member
1004 u32 num_lanes, in cdns_torrent_dp_set_power_state() argument
1031 switch (num_lanes) { in cdns_torrent_dp_set_power_state()
1065 static int cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy, u32 num_lanes) in cdns_torrent_dp_run() argument
1086 ret = cdns_torrent_dp_set_power_state(cdns_phy, num_lanes, in cdns_torrent_dp_run()
1091 ret = cdns_torrent_dp_set_power_state(cdns_phy, num_lanes, in cdns_torrent_dp_run()
1115 u32 rate, u32 num_lanes) in cdns_torrent_dp_pma_cmn_rate() argument
1153 for (i = 0; i < num_lanes; i++) in cdns_torrent_dp_pma_cmn_rate()
1247 if (dp->lanes > inst->num_lanes) in cdns_torrent_dp_verify_config()
1273 u32 num_lanes) in cdns_torrent_dp_set_a0_pll() argument
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| D | phy-cadence-sierra.c | 226 u32 num_lanes; member
274 u32 num_lanes; member
376 for (i = 0; i < ins->num_lanes; i++) { in cdns_sierra_phy_init()
610 if (of_property_read_u32(child, "cdns,num-lanes", &inst->num_lanes)) in cdns_sierra_get_optional()
948 sp->num_lanes += sp->phys[node].num_lanes; in cdns_sierra_phy_probe()
963 if (sp->num_lanes > SIERRA_MAX_LANES) { in cdns_sierra_phy_probe()
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| /drivers/gpu/drm/bridge/ |
| D | tc358767.c | 235 u8 num_lanes; member
442 if (tc->link.num_lanes == 2) in tc_srcctrl()
667 u8 revision, num_lanes; in tc_get_display_props() local
680 num_lanes = drm_dp_max_lane_count(tc->link.dpcd); in tc_get_display_props()
689 if (num_lanes > 2) { in tc_get_display_props()
691 num_lanes = 2; in tc_get_display_props()
694 tc->link.num_lanes = num_lanes; in tc_get_display_props()
715 tc->link.num_lanes, in tc_get_display_props()
756 out_bw = tc->link.num_lanes * tc->link.rate; in tc_set_video_mode()
928 if (tc->link.num_lanes == 2) in tc_main_link_enable()
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| D | sii902x.c | 757 int num_lanes, i; in sii902x_audio_codec_init() local
765 num_lanes = of_property_read_variable_u8_array(dev->of_node, in sii902x_audio_codec_init()
770 if (num_lanes == -EINVAL) { in sii902x_audio_codec_init()
774 num_lanes = 1; in sii902x_audio_codec_init()
776 } else if (num_lanes < 0) { in sii902x_audio_codec_init()
779 __func__, num_lanes); in sii902x_audio_codec_init()
780 return num_lanes; in sii902x_audio_codec_init()
782 codec_data.max_i2s_channels = 2 * num_lanes; in sii902x_audio_codec_init()
784 for (i = 0; i < num_lanes; i++) in sii902x_audio_codec_init()
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| /drivers/media/platform/exynos4-is/ |
| D | mipi-csis.c | 216 u32 num_lanes; member
322 mask = (1 << (state->num_lanes + 1)) - 1; in s5pcsis_system_enable()
360 val = (val & ~S5PCSIS_CFG_NR_LANE_MASK) | (state->num_lanes - 1); in s5pcsis_set_params()
754 state->num_lanes = endpoint.bus.mipi_csi2.num_data_lanes; in s5pcsis_parse_dt()
793 if (state->num_lanes == 0 || state->num_lanes > state->max_num_lanes) { in s5pcsis_probe()
795 state->num_lanes, state->max_num_lanes); in s5pcsis_probe()
877 state->num_lanes, state->hs_settle, state->wclk_ext, in s5pcsis_probe()
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| /drivers/gpu/drm/xlnx/ |
| D | zynqmp_dp.c | 312 u8 num_lanes; member
397 for (i = 0; i < dp->num_lanes; i++) { in zynqmp_dp_phy_init()
411 for (i = dp->num_lanes - 1; i >= 0; i--) { in zynqmp_dp_phy_init()
433 for (i = 0; i < dp->num_lanes; i++) { in zynqmp_dp_phy_exit()
440 for (i = 0; i < dp->num_lanes; i++) { in zynqmp_dp_phy_exit()
475 if (dp->num_lanes) in zynqmp_dp_phy_probe()
492 dp->num_lanes++; in zynqmp_dp_phy_probe()
511 ready = (1 << dp->num_lanes) - 1; in zynqmp_dp_phy_ready()
1318 dp->num_lanes); in zynqmp_dp_connector_detect()
1713 dp->num_lanes); in zynqmp_dp_probe()
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| /drivers/media/platform/rcar-vin/ |
| D | rcar-csi2.c | 505 unsigned int num_lanes = UINT_MAX; in rcsi2_get_active_lanes() local
529 num_lanes = 1; in rcsi2_get_active_lanes()
531 num_lanes = 2; in rcsi2_get_active_lanes()
533 num_lanes = 3; in rcsi2_get_active_lanes()
535 num_lanes = 4; in rcsi2_get_active_lanes()
537 if (num_lanes > priv->lanes) { in rcsi2_get_active_lanes()
540 num_lanes); in rcsi2_get_active_lanes()
544 *lanes = num_lanes; in rcsi2_get_active_lanes()
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| /drivers/media/platform/ti-vpe/ |
| D | cal-camerarx.c | 51 u32 num_lanes = mipi_csi2->num_data_lanes; in cal_camerarx_get_ext_link_freq() local
62 freq = v4l2_get_link_freq(phy->source->ctrl_handler, bpp, 2 * num_lanes); in cal_camerarx_get_ext_link_freq()
104 u32 num_lanes = phy->cal->data->camerarx[phy->instance].num_lanes; in cal_camerarx_enable() local
108 regmap_field_write(phy->fields[F_LANEENABLE], (1 << num_lanes) - 1); in cal_camerarx_enable()
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