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Searched refs:pipe_bpp (Results 1 – 21 of 21) sorted by relevance

/drivers/gpu/drm/i915/display/
Dintel_dp.c483 u32 pipe_bpp) in intel_dp_dsc_get_output_bpp() argument
532 bits_per_pixel = min(bits_per_pixel, pipe_bpp - 1); in intel_dp_dsc_get_output_bpp()
778 int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX); in intel_dp_mode_valid() local
794 pipe_bpp) >> 4; in intel_dp_mode_valid()
998 bpc = crtc_state->pipe_bpp / 3; in intel_dp_max_bpp()
1089 pipe_config->pipe_bpp = bpp; in intel_dp_compute_link_config_wide()
1200 int pipe_bpp; in intel_dp_dsc_compute_config() local
1209 pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc); in intel_dp_dsc_compute_config()
1212 if (pipe_bpp < 8 * 3) { in intel_dp_dsc_compute_config()
1223 pipe_config->pipe_bpp = pipe_bpp; in intel_dp_dsc_compute_config()
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Dg4x_hdmi.c40 if (crtc_state->pipe_bpp > 24) in intel_hdmi_prepare()
213 if (pipe_config->pipe_bpp > 24 && in ibx_enable_hdmi()
261 if (pipe_config->pipe_bpp > 24) { in cpt_enable_hdmi()
272 if (pipe_config->pipe_bpp > 24) { in cpt_enable_hdmi()
Dintel_fdi.c120 pipe_config->pipe_bpp); in ilk_fdi_compute_config()
124 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, in ilk_fdi_compute_config()
131 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { in ilk_fdi_compute_config()
132 pipe_config->pipe_bpp -= 2*3; in ilk_fdi_compute_config()
135 pipe_config->pipe_bpp); in ilk_fdi_compute_config()
Dintel_lvds.c290 if (pipe_config->dither && pipe_config->pipe_bpp == 18) in intel_pre_enable_lvds()
430 if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) { in intel_lvds_compute_config()
433 pipe_config->pipe_bpp, lvds_bpp); in intel_lvds_compute_config()
434 pipe_config->pipe_bpp = lvds_bpp; in intel_lvds_compute_config()
Dintel_dp_mst.c67 crtc_state->pipe_bpp = bpp; in intel_dp_mst_compute_link_config()
70 crtc_state->pipe_bpp, in intel_dp_mst_compute_link_config()
91 intel_link_compute_m_n(crtc_state->pipe_bpp, in intel_dp_mst_compute_link_config()
149 limits.max_bpp = min(pipe_config->pipe_bpp, 24); in intel_dp_mst_compute_config()
Dintel_hdmi.c933 static bool gcp_default_phase_possible(int pipe_bpp, in gcp_default_phase_possible() argument
938 switch (pipe_bpp) { in gcp_default_phase_possible()
1028 if (crtc_state->pipe_bpp > 24) in intel_hdmi_compute_gcp_infoframe()
1032 if (gcp_default_phase_possible(crtc_state->pipe_bpp, in intel_hdmi_compute_gcp_infoframe()
2005 if (crtc_state->pipe_bpp < bpc * 3) in intel_hdmi_deep_color_possible()
2090 if (crtc_state->pipe_bpp > bpc * 3) in intel_hdmi_compute_clock()
2091 crtc_state->pipe_bpp = bpc * 3; in intel_hdmi_compute_clock()
2095 bpc, crtc_state->pipe_bpp); in intel_hdmi_compute_clock()
Dintel_ddi.c328 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24) in ddi_dotclock_get()
329 dotclock = pipe_config->port_clock * 24 / pipe_config->pipe_bpp; in ddi_dotclock_get()
358 switch (crtc_state->pipe_bpp) { in intel_ddi_set_dp_msa()
372 MISSING_CASE(crtc_state->pipe_bpp); in intel_ddi_set_dp_msa()
435 switch (crtc_state->pipe_bpp) { in intel_ddi_transcoder_func_reg_val_get()
3523 pipe_config->pipe_bpp = 18; in intel_ddi_read_func_ctl()
3526 pipe_config->pipe_bpp = 24; in intel_ddi_read_func_ctl()
3529 pipe_config->pipe_bpp = 30; in intel_ddi_read_func_ctl()
3532 pipe_config->pipe_bpp = 36; in intel_ddi_read_func_ctl()
3636 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { in intel_ddi_get_config()
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Dg4x_dp.c400 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { in intel_dp_get_config()
416 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); in intel_dp_get_config()
417 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; in intel_dp_get_config()
Dintel_display.c4117 if (crtc_state->pipe_bpp > 24) in hsw_crtc_state_ips_capable()
4728 if (crtc_state->dither && crtc_state->pipe_bpp != 30) in i9xx_set_pipeconf()
4732 switch (crtc_state->pipe_bpp) { in i9xx_set_pipeconf()
4934 pipe_config->pipe_bpp = 18; in i9xx_get_pipe_config()
4937 pipe_config->pipe_bpp = 24; in i9xx_get_pipe_config()
4940 pipe_config->pipe_bpp = 30; in i9xx_get_pipe_config()
5543 switch (crtc_state->pipe_bpp) { in ilk_set_pipeconf()
5624 switch (crtc_state->pipe_bpp) { in bdw_set_pipemisc()
5640 MISSING_CASE(crtc_state->pipe_bpp); in bdw_set_pipemisc()
5901 pipe_config->pipe_bpp = 18; in ilk_get_pipe_config()
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Dintel_crt.c436 if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) { in hsw_crt_compute_config()
442 pipe_config->pipe_bpp = 24; in hsw_crt_compute_config()
Dicl_dsi.c1573 pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc); in gen11_dsi_get_config()
1618 if (crtc_state->pipe_bpp < 8 * 3) in gen11_dsi_dsc_compute_config()
1682 pipe_config->pipe_bpp = 24; in gen11_dsi_compute_config()
1684 pipe_config->pipe_bpp = 18; in gen11_dsi_compute_config()
Dintel_panel.c445 if (DISPLAY_VER(dev_priv) < 4 && crtc_state->pipe_bpp == 18) in intel_gmch_panel_fitting()
Dvlv_dsi.c299 pipe_config->pipe_bpp = 24; in intel_dsi_compute_config()
301 pipe_config->pipe_bpp = 18; in intel_dsi_compute_config()
1131 pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc); in bxt_dsi_get_pipe_config()
Dintel_audio.c276 if (crtc_state->pipe_bpp == 36) { in audio_config_hdmi_get_n()
279 } else if (crtc_state->pipe_bpp == 30) { in audio_config_hdmi_get_n()
Dintel_psr.c959 if (crtc_state->pipe_bpp > max_bpp) { in intel_psr2_config_valid()
962 crtc_state->pipe_bpp, max_bpp); in intel_psr2_config_valid()
Dintel_vdsc.c469 vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3; in intel_dsc_compute_params()
Dintel_bios.c2787 crtc_state->pipe_bpp = bpc * 3; in fill_dsc()
2789 crtc_state->dsc.compressed_bpp = min(crtc_state->pipe_bpp, in fill_dsc()
Dintel_display_types.h1056 int pipe_bpp; member
Dintel_tv.c1205 pipe_config->pipe_bpp = 8*3; in intel_tv_compute_config()
Dintel_display_debugfs.c1030 yesno(crtc_state->dither), crtc_state->pipe_bpp); in intel_crtc_info()
Dintel_sdvo.c1316 pipe_config->pipe_bpp = 8*3; in intel_sdvo_compute_config()