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Searched refs:pool (Results 1 – 25 of 281) sorted by relevance

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/drivers/md/
Ddm-thin.c229 struct pool { struct
289 static void metadata_operation_failed(struct pool *pool, const char *op, int r); argument
291 static enum pool_mode get_pool_mode(struct pool *pool) in get_pool_mode() argument
293 return pool->pf.mode; in get_pool_mode()
296 static void notify_of_pool_mode_change(struct pool *pool) in notify_of_pool_mode_change() argument
306 enum pool_mode mode = get_pool_mode(pool); in notify_of_pool_mode_change()
309 if (!pool->pf.error_if_no_space) in notify_of_pool_mode_change()
315 dm_table_event(pool->ti->table); in notify_of_pool_mode_change()
317 dm_device_name(pool->pool_md), in notify_of_pool_mode_change()
326 struct pool *pool; member
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/drivers/net/ethernet/ti/
Dk3-cppi-desc-pool.c27 void k3_cppi_desc_pool_destroy(struct k3_cppi_desc_pool *pool) in k3_cppi_desc_pool_destroy() argument
29 if (!pool) in k3_cppi_desc_pool_destroy()
32 WARN(gen_pool_size(pool->gen_pool) != gen_pool_avail(pool->gen_pool), in k3_cppi_desc_pool_destroy()
34 gen_pool_size(pool->gen_pool), in k3_cppi_desc_pool_destroy()
35 gen_pool_avail(pool->gen_pool)); in k3_cppi_desc_pool_destroy()
36 if (pool->cpumem) in k3_cppi_desc_pool_destroy()
37 dma_free_coherent(pool->dev, pool->mem_size, pool->cpumem, in k3_cppi_desc_pool_destroy()
38 pool->dma_addr); in k3_cppi_desc_pool_destroy()
40 gen_pool_destroy(pool->gen_pool); /* frees pool->name */ in k3_cppi_desc_pool_destroy()
48 struct k3_cppi_desc_pool *pool; in k3_cppi_desc_pool_create_name() local
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/drivers/infiniband/sw/rxe/
Drxe_pool.c89 static inline const char *pool_name(struct rxe_pool *pool) in pool_name() argument
91 return rxe_type_info[pool->type].name; in pool_name()
94 static int rxe_pool_init_index(struct rxe_pool *pool, u32 max, u32 min) in rxe_pool_init_index() argument
99 if ((max - min + 1) < pool->max_elem) { in rxe_pool_init_index()
105 pool->index.max_index = max; in rxe_pool_init_index()
106 pool->index.min_index = min; in rxe_pool_init_index()
109 pool->index.table = kmalloc(size, GFP_KERNEL); in rxe_pool_init_index()
110 if (!pool->index.table) { in rxe_pool_init_index()
115 pool->index.table_size = size; in rxe_pool_init_index()
116 bitmap_zero(pool->index.table, max - min + 1); in rxe_pool_init_index()
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/drivers/dma-buf/heaps/
Dpage_pool.c20 struct dmabuf_page_pool pool; member
28 struct page *dmabuf_page_pool_alloc_pages(struct dmabuf_page_pool *pool) in dmabuf_page_pool_alloc_pages() argument
32 return alloc_pages(pool->gfp_mask, pool->order); in dmabuf_page_pool_alloc_pages()
35 static inline void dmabuf_page_pool_free_pages(struct dmabuf_page_pool *pool, in dmabuf_page_pool_free_pages() argument
38 __free_pages(page, pool->order); in dmabuf_page_pool_free_pages()
41 static void dmabuf_page_pool_add(struct dmabuf_page_pool *pool, struct page *page) in dmabuf_page_pool_add() argument
45 container_of(pool, struct dmabuf_page_pool_with_spinlock, pool); in dmabuf_page_pool_add()
53 list_add_tail(&page->lru, &pool->items[index]); in dmabuf_page_pool_add()
54 pool->count[index]++; in dmabuf_page_pool_add()
57 1 << pool->order); in dmabuf_page_pool_add()
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/drivers/gpu/drm/amd/display/dc/dce80/
Ddce80_resource.c801 static void dce80_resource_destruct(struct dce110_resource_pool *pool) in dce80_resource_destruct() argument
805 for (i = 0; i < pool->base.pipe_count; i++) { in dce80_resource_destruct()
806 if (pool->base.opps[i] != NULL) in dce80_resource_destruct()
807 dce110_opp_destroy(&pool->base.opps[i]); in dce80_resource_destruct()
809 if (pool->base.transforms[i] != NULL) in dce80_resource_destruct()
810 dce80_transform_destroy(&pool->base.transforms[i]); in dce80_resource_destruct()
812 if (pool->base.ipps[i] != NULL) in dce80_resource_destruct()
813 dce_ipp_destroy(&pool->base.ipps[i]); in dce80_resource_destruct()
815 if (pool->base.mis[i] != NULL) { in dce80_resource_destruct()
816 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); in dce80_resource_destruct()
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/drivers/gpu/drm/amd/display/dc/dce60/
Ddce60_resource.c796 static void dce60_resource_destruct(struct dce110_resource_pool *pool) in dce60_resource_destruct() argument
800 for (i = 0; i < pool->base.pipe_count; i++) { in dce60_resource_destruct()
801 if (pool->base.opps[i] != NULL) in dce60_resource_destruct()
802 dce110_opp_destroy(&pool->base.opps[i]); in dce60_resource_destruct()
804 if (pool->base.transforms[i] != NULL) in dce60_resource_destruct()
805 dce60_transform_destroy(&pool->base.transforms[i]); in dce60_resource_destruct()
807 if (pool->base.ipps[i] != NULL) in dce60_resource_destruct()
808 dce_ipp_destroy(&pool->base.ipps[i]); in dce60_resource_destruct()
810 if (pool->base.mis[i] != NULL) { in dce60_resource_destruct()
811 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); in dce60_resource_destruct()
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/drivers/staging/media/atomisp/pci/runtime/rmgr/src/
Drmgr_vbuf.c128 int ia_css_rmgr_init_vbuf(struct ia_css_rmgr_vbuf_pool *pool) in ia_css_rmgr_init_vbuf() argument
134 assert(pool); in ia_css_rmgr_init_vbuf()
135 if (!pool) in ia_css_rmgr_init_vbuf()
138 if (pool->recycle && pool->size) { in ia_css_rmgr_init_vbuf()
142 pool->size; in ia_css_rmgr_init_vbuf()
143 pool->handles = kvmalloc(bytes_needed, GFP_KERNEL); in ia_css_rmgr_init_vbuf()
144 if (pool->handles) in ia_css_rmgr_init_vbuf()
145 memset(pool->handles, 0, bytes_needed); in ia_css_rmgr_init_vbuf()
150 pool->size = 0; in ia_css_rmgr_init_vbuf()
151 pool->handles = NULL; in ia_css_rmgr_init_vbuf()
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/drivers/net/ethernet/mellanox/mlxsw/
Dspectrum_cnt.c54 struct mlxsw_sp_counter_pool *pool = mlxsw_sp->counter_pool; in mlxsw_sp_counter_sub_pools_init() local
62 for (i = 0; i < pool->sub_pools_count; i++) { in mlxsw_sp_counter_sub_pools_init()
63 sub_pool = &pool->sub_pools[i]; in mlxsw_sp_counter_sub_pools_init()
89 sub_pool = &pool->sub_pools[i]; in mlxsw_sp_counter_sub_pools_init()
99 struct mlxsw_sp_counter_pool *pool = mlxsw_sp->counter_pool; in mlxsw_sp_counter_sub_pools_fini() local
104 for (i = 0; i < pool->sub_pools_count; i++) { in mlxsw_sp_counter_sub_pools_fini()
105 sub_pool = &pool->sub_pools[i]; in mlxsw_sp_counter_sub_pools_fini()
115 const struct mlxsw_sp_counter_pool *pool = priv; in mlxsw_sp_counter_pool_occ_get() local
117 return atomic_read(&pool->active_entries_count); in mlxsw_sp_counter_pool_occ_get()
124 struct mlxsw_sp_counter_pool *pool; in mlxsw_sp_counter_pool_init() local
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/drivers/gpu/drm/i915/gt/
Dintel_gt_buffer_pool.c12 static struct intel_gt *to_gt(struct intel_gt_buffer_pool *pool) in to_gt() argument
14 return container_of(pool, struct intel_gt, buffer_pool); in to_gt()
18 bucket_for_size(struct intel_gt_buffer_pool *pool, size_t sz) in bucket_for_size() argument
28 if (n >= ARRAY_SIZE(pool->cache_list)) in bucket_for_size()
29 n = ARRAY_SIZE(pool->cache_list) - 1; in bucket_for_size()
31 return &pool->cache_list[n]; in bucket_for_size()
41 static bool pool_free_older_than(struct intel_gt_buffer_pool *pool, long keep) in pool_free_older_than() argument
48 for (n = 0; n < ARRAY_SIZE(pool->cache_list); n++) { in pool_free_older_than()
49 struct list_head *list = &pool->cache_list[n]; in pool_free_older_than()
54 if (spin_trylock_irq(&pool->lock)) { in pool_free_older_than()
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/drivers/net/ethernet/mellanox/mlx5/core/steering/
Ddr_icm_pool.c61 dr_icm_pool_mr_create(struct mlx5dr_icm_pool *pool) in dr_icm_pool_mr_create() argument
63 struct mlx5_core_dev *mdev = pool->dmn->mdev; in dr_icm_pool_mr_create()
73 icm_mr->dmn = pool->dmn; in dr_icm_pool_mr_create()
75 icm_mr->dm.length = mlx5dr_icm_pool_chunk_size_to_byte(pool->max_log_chunk_sz, in dr_icm_pool_mr_create()
76 pool->icm_type); in dr_icm_pool_mr_create()
78 if (pool->icm_type == DR_ICM_TYPE_STE) { in dr_icm_pool_mr_create()
92 mlx5dr_err(pool->dmn, "Failed to allocate SW ICM memory, err (%d)\n", err); in dr_icm_pool_mr_create()
97 err = dr_icm_create_dm_mkey(mdev, pool->dmn->pdn, in dr_icm_pool_mr_create()
103 mlx5dr_err(pool->dmn, "Failed to create SW ICM MKEY, err (%d)\n", err); in dr_icm_pool_mr_create()
110 mlx5dr_err(pool->dmn, "Failed to get Aligned ICM mem (asked: %zu)\n", in dr_icm_pool_mr_create()
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/drivers/media/platform/vsp1/
Dvsp1_dl.c110 struct vsp1_dl_body_pool *pool; member
227 struct vsp1_dl_body_pool *pool; member
251 struct vsp1_dl_body_pool *pool; in vsp1_dl_body_pool_create() local
255 pool = kzalloc(sizeof(*pool), GFP_KERNEL); in vsp1_dl_body_pool_create()
256 if (!pool) in vsp1_dl_body_pool_create()
259 pool->vsp1 = vsp1; in vsp1_dl_body_pool_create()
268 pool->size = dlb_size * num_bodies; in vsp1_dl_body_pool_create()
270 pool->bodies = kcalloc(num_bodies, sizeof(*pool->bodies), GFP_KERNEL); in vsp1_dl_body_pool_create()
271 if (!pool->bodies) { in vsp1_dl_body_pool_create()
272 kfree(pool); in vsp1_dl_body_pool_create()
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/drivers/net/ethernet/mellanox/mlx5/core/
Dpci_irq.c34 struct mlx5_irq_pool *pool; member
153 struct mlx5_irq_pool *pool = irq->pool; in irq_release() local
155 xa_erase(&pool->irqs, irq->index); in irq_release()
163 struct mlx5_irq_pool *pool = irq->pool; in irq_put() local
165 mutex_lock(&pool->lock); in irq_put()
169 mutex_unlock(&pool->lock); in irq_put()
174 lockdep_assert_held(&irq->pool->lock); in irq_get_locked()
185 mutex_lock(&irq->pool->lock); in irq_get()
187 mutex_unlock(&irq->pool->lock); in irq_get()
197 static void irq_sf_set_name(struct mlx5_irq_pool *pool, char *name, int vecidx) in irq_sf_set_name() argument
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/drivers/gpu/drm/amd/display/dc/dce100/
Ddce100_resource.c753 static void dce100_resource_destruct(struct dce110_resource_pool *pool) in dce100_resource_destruct() argument
757 for (i = 0; i < pool->base.pipe_count; i++) { in dce100_resource_destruct()
758 if (pool->base.opps[i] != NULL) in dce100_resource_destruct()
759 dce110_opp_destroy(&pool->base.opps[i]); in dce100_resource_destruct()
761 if (pool->base.transforms[i] != NULL) in dce100_resource_destruct()
762 dce100_transform_destroy(&pool->base.transforms[i]); in dce100_resource_destruct()
764 if (pool->base.ipps[i] != NULL) in dce100_resource_destruct()
765 dce_ipp_destroy(&pool->base.ipps[i]); in dce100_resource_destruct()
767 if (pool->base.mis[i] != NULL) { in dce100_resource_destruct()
768 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); in dce100_resource_destruct()
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/drivers/gpu/drm/amd/display/dc/dcn303/
Ddcn303_resource.c784 static bool dcn303_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) in dcn303_dwbc_create() argument
787 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn303_dwbc_create()
799 pool->dwbc[i] = &dwbc30->base; in dcn303_dwbc_create()
819 static bool dcn303_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) in dcn303_mmhubbub_create() argument
822 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn303_mmhubbub_create()
834 pool->mcif_wb[i] = &mcif_wb30->base; in dcn303_mmhubbub_create()
1019 static bool init_soc_bounding_box(struct dc *dc, struct resource_pool *pool) in init_soc_bounding_box() argument
1031 loaded_ip->max_num_otg = pool->pipe_count; in init_soc_bounding_box()
1032 loaded_ip->max_num_dpp = pool->pipe_count; in init_soc_bounding_box()
1058 static void dcn303_resource_destruct(struct resource_pool *pool) in dcn303_resource_destruct() argument
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/drivers/gpu/drm/amd/display/dc/dcn302/
Ddcn302_resource.c842 static bool dcn302_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) in dcn302_dwbc_create() argument
845 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn302_dwbc_create()
857 pool->dwbc[i] = &dwbc30->base; in dcn302_dwbc_create()
877 static bool dcn302_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) in dcn302_mmhubbub_create() argument
880 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn302_mmhubbub_create()
892 pool->mcif_wb[i] = &mcif_wb30->base; in dcn302_mmhubbub_create()
1093 static bool init_soc_bounding_box(struct dc *dc, struct resource_pool *pool) in init_soc_bounding_box() argument
1105 loaded_ip->max_num_otg = pool->pipe_count; in init_soc_bounding_box()
1106 loaded_ip->max_num_dpp = pool->pipe_count; in init_soc_bounding_box()
1132 static void dcn302_resource_destruct(struct resource_pool *pool) in dcn302_resource_destruct() argument
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/drivers/staging/media/ipu3/
Dipu3-css-pool.c25 void imgu_css_pool_cleanup(struct imgu_device *imgu, struct imgu_css_pool *pool) in imgu_css_pool_cleanup() argument
30 imgu_dmamap_free(imgu, &pool->entry[i].param); in imgu_css_pool_cleanup()
33 int imgu_css_pool_init(struct imgu_device *imgu, struct imgu_css_pool *pool, in imgu_css_pool_init() argument
39 pool->entry[i].valid = false; in imgu_css_pool_init()
41 pool->entry[i].param.vaddr = NULL; in imgu_css_pool_init()
45 if (!imgu_dmamap_alloc(imgu, &pool->entry[i].param, size)) in imgu_css_pool_init()
49 pool->last = IPU3_CSS_POOL_SIZE; in imgu_css_pool_init()
54 imgu_css_pool_cleanup(imgu, pool); in imgu_css_pool_init()
61 void imgu_css_pool_get(struct imgu_css_pool *pool) in imgu_css_pool_get() argument
64 u32 n = (pool->last + 1) % IPU3_CSS_POOL_SIZE; in imgu_css_pool_get()
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/drivers/staging/octeon/
Dethernet-mem.c24 static int cvm_oct_fill_hw_skbuff(int pool, int size, int elements) in cvm_oct_fill_hw_skbuff() argument
35 cvmx_fpa_free(skb->data, pool, size / 128); in cvm_oct_fill_hw_skbuff()
47 static void cvm_oct_free_hw_skbuff(int pool, int size, int elements) in cvm_oct_free_hw_skbuff() argument
52 memory = cvmx_fpa_alloc(pool); in cvm_oct_free_hw_skbuff()
63 pool, elements); in cvm_oct_free_hw_skbuff()
66 pool, elements); in cvm_oct_free_hw_skbuff()
77 static int cvm_oct_fill_hw_memory(int pool, int size, int elements) in cvm_oct_fill_hw_memory() argument
97 elements * size, pool); in cvm_oct_fill_hw_memory()
102 cvmx_fpa_free(fpa, pool, 0); in cvm_oct_fill_hw_memory()
114 static void cvm_oct_free_hw_memory(int pool, int size, int elements) in cvm_oct_free_hw_memory() argument
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/drivers/net/ethernet/mellanox/mlx5/core/en/xsk/
Dpool.c10 struct xsk_buff_pool *pool) in mlx5e_xsk_map_pool() argument
14 return xsk_pool_dma_map(pool, dev, DMA_ATTR_SKIP_CPU_SYNC); in mlx5e_xsk_map_pool()
18 struct xsk_buff_pool *pool) in mlx5e_xsk_unmap_pool() argument
20 return xsk_pool_dma_unmap(pool, DMA_ATTR_SKIP_CPU_SYNC); in mlx5e_xsk_unmap_pool()
46 static int mlx5e_xsk_add_pool(struct mlx5e_xsk *xsk, struct xsk_buff_pool *pool, u16 ix) in mlx5e_xsk_add_pool() argument
54 xsk->pools[ix] = pool; in mlx5e_xsk_add_pool()
65 static bool mlx5e_xsk_is_pool_sane(struct xsk_buff_pool *pool) in mlx5e_xsk_is_pool_sane() argument
67 return xsk_pool_get_headroom(pool) <= 0xffff && in mlx5e_xsk_is_pool_sane()
68 xsk_pool_get_chunk_size(pool) <= 0xffff; in mlx5e_xsk_is_pool_sane()
71 void mlx5e_build_xsk_param(struct xsk_buff_pool *pool, struct mlx5e_xsk_param *xsk) in mlx5e_build_xsk_param() argument
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/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_resource.c965 static void dcn10_resource_destruct(struct dcn10_resource_pool *pool) in dcn10_resource_destruct() argument
969 for (i = 0; i < pool->base.stream_enc_count; i++) { in dcn10_resource_destruct()
970 if (pool->base.stream_enc[i] != NULL) { in dcn10_resource_destruct()
971 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); in dcn10_resource_destruct()
972 pool->base.stream_enc[i] = NULL; in dcn10_resource_destruct()
976 if (pool->base.mpc != NULL) { in dcn10_resource_destruct()
977 kfree(TO_DCN10_MPC(pool->base.mpc)); in dcn10_resource_destruct()
978 pool->base.mpc = NULL; in dcn10_resource_destruct()
981 if (pool->base.hubbub != NULL) { in dcn10_resource_destruct()
982 kfree(pool->base.hubbub); in dcn10_resource_destruct()
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/drivers/gpu/drm/amd/display/dc/dce120/
Ddce120_resource.c597 static void dce120_resource_destruct(struct dce110_resource_pool *pool) in dce120_resource_destruct() argument
601 for (i = 0; i < pool->base.pipe_count; i++) { in dce120_resource_destruct()
602 if (pool->base.opps[i] != NULL) in dce120_resource_destruct()
603 dce110_opp_destroy(&pool->base.opps[i]); in dce120_resource_destruct()
605 if (pool->base.transforms[i] != NULL) in dce120_resource_destruct()
606 dce120_transform_destroy(&pool->base.transforms[i]); in dce120_resource_destruct()
608 if (pool->base.ipps[i] != NULL) in dce120_resource_destruct()
609 dce_ipp_destroy(&pool->base.ipps[i]); in dce120_resource_destruct()
611 if (pool->base.mis[i] != NULL) { in dce120_resource_destruct()
612 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); in dce120_resource_destruct()
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/drivers/gpu/drm/amd/display/dc/dce110/
Ddce110_resource.c812 static void dce110_resource_destruct(struct dce110_resource_pool *pool) in dce110_resource_destruct() argument
816 for (i = 0; i < pool->base.pipe_count; i++) { in dce110_resource_destruct()
817 if (pool->base.opps[i] != NULL) in dce110_resource_destruct()
818 dce110_opp_destroy(&pool->base.opps[i]); in dce110_resource_destruct()
820 if (pool->base.transforms[i] != NULL) in dce110_resource_destruct()
821 dce110_transform_destroy(&pool->base.transforms[i]); in dce110_resource_destruct()
823 if (pool->base.ipps[i] != NULL) in dce110_resource_destruct()
824 dce_ipp_destroy(&pool->base.ipps[i]); in dce110_resource_destruct()
826 if (pool->base.mis[i] != NULL) { in dce110_resource_destruct()
827 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); in dce110_resource_destruct()
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/drivers/gpu/drm/amd/display/dc/dcn301/
Ddcn301_resource.c89 #define TO_DCN301_RES_POOL(pool)\ argument
90 container_of(pool, struct dcn301_resource_pool, base)
1240 static void dcn301_destruct(struct dcn301_resource_pool *pool) in dcn301_destruct() argument
1244 for (i = 0; i < pool->base.stream_enc_count; i++) { in dcn301_destruct()
1245 if (pool->base.stream_enc[i] != NULL) { in dcn301_destruct()
1246 if (pool->base.stream_enc[i]->vpg != NULL) { in dcn301_destruct()
1247 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)); in dcn301_destruct()
1248 pool->base.stream_enc[i]->vpg = NULL; in dcn301_destruct()
1250 if (pool->base.stream_enc[i]->afmt != NULL) { in dcn301_destruct()
1251 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt)); in dcn301_destruct()
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/drivers/gpu/drm/ttm/
Dttm_pool.c78 static struct page *ttm_pool_alloc_page(struct ttm_pool *pool, gfp_t gfp_flags, in ttm_pool_alloc_page() argument
94 if (!pool->use_dma_alloc) { in ttm_pool_alloc_page()
108 vaddr = dma_alloc_attrs(pool->dev, (1ULL << order) * PAGE_SIZE, in ttm_pool_alloc_page()
131 static void ttm_pool_free_page(struct ttm_pool *pool, enum ttm_caching caching, in ttm_pool_free_page() argument
146 if (!pool || !pool->use_dma_alloc) { in ttm_pool_free_page()
156 dma_free_attrs(pool->dev, (1UL << order) * PAGE_SIZE, vaddr, dma->addr, in ttm_pool_free_page()
184 static int ttm_pool_map(struct ttm_pool *pool, unsigned int order, in ttm_pool_map() argument
190 if (pool->use_dma_alloc) { in ttm_pool_map()
197 addr = dma_map_page(pool->dev, p, 0, size, DMA_BIDIRECTIONAL); in ttm_pool_map()
198 if (dma_mapping_error(pool->dev, addr)) in ttm_pool_map()
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/drivers/crypto/hisilicon/
Dsgl.c60 struct hisi_acc_sgl_pool *pool; in hisi_acc_create_sgl_pool() local
84 pool = kzalloc(sizeof(*pool), GFP_KERNEL); in hisi_acc_create_sgl_pool()
85 if (!pool) in hisi_acc_create_sgl_pool()
87 block = pool->mem_block; in hisi_acc_create_sgl_pool()
113 pool->sgl_num_per_block = sgl_num_per_block; in hisi_acc_create_sgl_pool()
114 pool->block_num = remain_sgl ? block_num + 1 : block_num; in hisi_acc_create_sgl_pool()
115 pool->count = count; in hisi_acc_create_sgl_pool()
116 pool->sgl_size = sgl_size; in hisi_acc_create_sgl_pool()
117 pool->sge_nr = sge_nr; in hisi_acc_create_sgl_pool()
119 return pool; in hisi_acc_create_sgl_pool()
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/drivers/gpu/drm/amd/display/dc/dce112/
Ddce112_resource.c774 static void dce112_resource_destruct(struct dce110_resource_pool *pool) in dce112_resource_destruct() argument
778 for (i = 0; i < pool->base.pipe_count; i++) { in dce112_resource_destruct()
779 if (pool->base.opps[i] != NULL) in dce112_resource_destruct()
780 dce110_opp_destroy(&pool->base.opps[i]); in dce112_resource_destruct()
782 if (pool->base.transforms[i] != NULL) in dce112_resource_destruct()
783 dce112_transform_destroy(&pool->base.transforms[i]); in dce112_resource_destruct()
785 if (pool->base.ipps[i] != NULL) in dce112_resource_destruct()
786 dce_ipp_destroy(&pool->base.ipps[i]); in dce112_resource_destruct()
788 if (pool->base.mis[i] != NULL) { in dce112_resource_destruct()
789 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); in dce112_resource_destruct()
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