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Searched refs:rd_reg_dword (Results 1 – 16 of 16) sorted by relevance

/drivers/scsi/qla2xxx/
Dqla_dbg.c148 stat = rd_reg_dword(&reg->host_status); in qla27xx_dump_mpi_ram()
159 rd_reg_dword(&reg->hccr); in qla27xx_dump_mpi_ram()
166 rd_reg_dword(&reg->hccr); in qla27xx_dump_mpi_ram()
233 stat = rd_reg_dword(&reg->host_status); in qla24xx_dump_ram()
242 rd_reg_dword(&reg->hccr); in qla24xx_dump_ram()
249 rd_reg_dword(&reg->hccr); in qla24xx_dump_ram()
305 *buf++ = htonl(rd_reg_dword(dmp_reg)); in qla24xx_read_window()
317 if (rd_reg_dword(&reg->host_status) & HSRX_RISC_PAUSED) in qla24xx_pause_risc()
336 if ((rd_reg_dword(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0) in qla24xx_soft_reset()
341 if (!(rd_reg_dword(&reg->ctrl_status) & CSRX_DMA_ACTIVE)) in qla24xx_soft_reset()
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Dqla_mr.c685 rd_reg_dword(&reg->rsp_q_out); in qlafx00_config_rings()
891 pseudo_aen = rd_reg_dword(&reg->pseudoaen); in qlafx00_init_fw_ready()
893 aenmbx7 = rd_reg_dword(&reg->initval7); in qlafx00_init_fw_ready()
904 aenmbx = rd_reg_dword(&reg->aenmailbox0); in qlafx00_init_fw_ready()
923 aenmbx7 = rd_reg_dword(&reg->aenmailbox7); in qlafx00_init_fw_ready()
926 ha->req_que_off = rd_reg_dword(&reg->aenmailbox1); in qlafx00_init_fw_ready()
927 ha->rsp_que_off = rd_reg_dword(&reg->aenmailbox3); in qlafx00_init_fw_ready()
928 ha->req_que_len = rd_reg_dword(&reg->aenmailbox5); in qlafx00_init_fw_ready()
929 ha->rsp_que_len = rd_reg_dword(&reg->aenmailbox6); in qlafx00_init_fw_ready()
961 aenmbx7 = rd_reg_dword(&reg->initval7); in qlafx00_init_fw_ready()
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Dqla_mr.h373 rd_reg_dword((ha)->cregbase + QLAFX00_HBA_TO_HOST_REG)
383 rd_reg_dword((ha)->cregbase + off)
389 rd_reg_dword((ha)->cregbase + QLAFX00_HBA_ICNTRL_REG)
402 rd_reg_dword((ha)->cregbase + off)
Dqla_sup.c461 if (rd_reg_dword(&reg->flash_addr) & FARX_DATA_FLAG) { in qla24xx_read_flash_dword()
462 *data = rd_reg_dword(&reg->flash_data); in qla24xx_read_flash_dword()
505 if (!(rd_reg_dword(&reg->flash_addr) & FARX_DATA_FLAG)) in qla24xx_write_flash_dword()
1202 rd_reg_dword(&reg->ctrl_status) | CSRX_FLASH_ENABLE); in qla24xx_unprotect_flash()
1203 rd_reg_dword(&reg->ctrl_status); /* PCI Posting. */ in qla24xx_unprotect_flash()
1245 rd_reg_dword(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE); in qla24xx_protect_flash()
1471 rd_reg_dword(&reg->ctrl_status) | CSRX_FLASH_ENABLE); in qla24xx_write_nvram_data()
1472 rd_reg_dword(&reg->ctrl_status); /* PCI Posting. */ in qla24xx_write_nvram_data()
1495 rd_reg_dword(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE); in qla24xx_write_nvram_data()
1496 rd_reg_dword(&reg->ctrl_status); /* PCI Posting. */ in qla24xx_write_nvram_data()
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Dqla_inline.h538 return ((rd_reg_dword(&reg82->host_int)) == ISP_REG_DISCONNECT); in qla2x00_isp_reg_stat()
540 return ((rd_reg_dword(&reg->host_status)) == in qla2x00_isp_reg_stat()
551 stat = rd_reg_dword(&reg->host_status); in qla_pci_disconnected()
Dqla_nx.c372 win_read = rd_reg_dword(CRB_WINDOW_2M + ha->nx_pcibase); in qla82xx_pci_set_crbwindow_2M()
481 data = rd_reg_dword(off); in qla82xx_rd_32()
898 rd_reg_dword(CRB_WINDOW_2M + ha->nx_pcibase); in qla82xx_md_rw_32()
905 rval = rd_reg_dword(off_value + CRB_INDIRECT_2M + in qla82xx_md_rw_32()
2025 if (rd_reg_dword(&reg->host_int)) { in qla82xx_intr_handler()
2026 stat = rd_reg_dword(&reg->host_status); in qla82xx_intr_handler()
2091 host_int = rd_reg_dword(&reg->host_int); in qla82xx_msix_default()
2095 stat = rd_reg_dword(&reg->host_status); in qla82xx_msix_default()
2152 host_int = rd_reg_dword(&reg->host_int); in qla82xx_msix_rsp_q()
2186 host_int = rd_reg_dword(&reg->host_int); in qla82xx_poll()
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Dqla_isr.c466 stat = rd_reg_dword(&reg->u.isp2300.host_status); in qla2300_intr_handler()
3993 rd_reg_dword(&reg->iobase_addr); in qla2xxx_check_risc_status()
3995 for (cnt = 10000; (rd_reg_dword(&reg->iobase_window) & BIT_0) == 0 && in qla2xxx_check_risc_status()
4008 for (cnt = 100; (rd_reg_dword(&reg->iobase_window) & BIT_0) == 0 && in qla2xxx_check_risc_status()
4020 if (rd_reg_dword(&reg->iobase_c8) & BIT_3) in qla2xxx_check_risc_status()
4026 rd_reg_dword(&reg->iobase_window); in qla2xxx_check_risc_status()
4070 stat = rd_reg_dword(&reg->host_status); in qla24xx_intr_handler()
4077 hccr = rd_reg_dword(&reg->hccr); in qla24xx_intr_handler()
4199 stat = rd_reg_dword(&reg->host_status); in qla24xx_msix_default()
4206 hccr = rd_reg_dword(&reg->hccr); in qla24xx_msix_default()
Dqla_init.c2987 ha->pci_attr = rd_reg_dword(&reg->ctrl_status); in qla24xx_pci_config()
3290 if ((rd_reg_dword(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0) in qla24xx_reset_risc()
3296 if (!(rd_reg_dword(&reg->ctrl_status) & CSRX_DMA_ACTIVE)) in qla24xx_reset_risc()
3301 rd_reg_dword(&reg->hccr), in qla24xx_reset_risc()
3302 rd_reg_dword(&reg->ctrl_status), in qla24xx_reset_risc()
3303 (rd_reg_dword(&reg->ctrl_status) & CSRX_DMA_ACTIVE)); in qla24xx_reset_risc()
3327 rd_reg_dword(&reg->hccr), in qla24xx_reset_risc()
3331 rd_reg_dword(&reg->ctrl_status); in qla24xx_reset_risc()
3334 if ((rd_reg_dword(&reg->ctrl_status) & in qla24xx_reset_risc()
3340 if (!(rd_reg_dword(&reg->ctrl_status) & CSRX_ISP_SOFT_RESET)) in qla24xx_reset_risc()
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Dqla_mbx.c315 if (rd_reg_dword(&reg->isp82.hint) & in qla2x00_mailbox_command()
428 ictrl = rd_reg_dword(&reg->isp24.ictrl); in qla2x00_mailbox_command()
429 host_status = rd_reg_dword(&reg->isp24.host_status); in qla2x00_mailbox_command()
430 hccr = rd_reg_dword(&reg->isp24.hccr); in qla2x00_mailbox_command()
588 rd_reg_dword(&reg->isp24.host_status), in qla2x00_mailbox_command()
589 rd_reg_dword(&reg->isp24.ictrl), in qla2x00_mailbox_command()
590 rd_reg_dword(&reg->isp24.istatus)); in qla2x00_mailbox_command()
5523 stat = rd_reg_dword(&reg->host_status); in qla81xx_write_mpi_register()
5534 rd_reg_dword(&reg->hccr); in qla81xx_write_mpi_register()
Dqla_iocb.c2308 cnt = rd_reg_dword(&reg->isp25mq.req_q_out); in __qla2x00_alloc_iocbs()
2310 cnt = rd_reg_dword(reg->isp82.req_q_out); in __qla2x00_alloc_iocbs()
2312 cnt = rd_reg_dword(&reg->isp24.req_q_out); in __qla2x00_alloc_iocbs()
2314 cnt = rd_reg_dword(&reg->ispfx00.req_q_out); in __qla2x00_alloc_iocbs()
3644 while (rd_reg_dword(ha->nxdb_rd_ptr) != dbval) { in qla82xx_start_scsi()
Dqla_tmpl.c72 value = rd_reg_dword(window); in qla27xx_read32()
Dqla_nx2.c3940 if (rd_reg_dword(&reg->host_int)) { in qla8044_intr_handler()
3941 stat = rd_reg_dword(&reg->host_status); in qla8044_intr_handler()
Dqla_os.c2026 rd_reg_dword(&reg->ictrl); in qla24xx_enable_intrs()
2041 rd_reg_dword(&reg->ictrl); in qla24xx_disable_intrs()
7825 stat = rd_reg_dword(&reg->u.isp2300.host_status); in qla2xxx_pci_mmio_enabled()
7829 stat = rd_reg_dword(&reg24->host_status); in qla2xxx_pci_mmio_enabled()
Dqla_edif.c2910 rd_reg_dword(req->req_q_out); in qla28xx_start_scsi_edif()
Dqla_def.h164 static inline u32 rd_reg_dword(const volatile __le32 __iomem *addr) in rd_reg_dword() function
Dqla_target.c6961 rd_reg_dword(ISP_ATIO_Q_OUT(vha)); in qlt_24xx_config_rings()