| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
| D | dcn31_clk_mgr.c | 425 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in dcn31_build_watermark_ranges()
441 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in dcn31_build_watermark_ranges()
444 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF; in dcn31_build_watermark_ranges()
455 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF; in dcn31_build_watermark_ranges()
460 table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF; in dcn31_build_watermark_ranges()
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| D | dcn31_smu.h | 53 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz) member
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| D | vg_clk_mgr.c | 413 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in vg_build_watermark_ranges()
429 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in vg_build_watermark_ranges()
432 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF; in vg_build_watermark_ranges()
443 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF; in vg_build_watermark_ranges()
448 table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF; in vg_build_watermark_ranges()
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| D | dcn301_smu.h | 57 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz) member
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| /drivers/gpu/drm/amd/pm/inc/ |
| D | smu10_driver_if.h | 52 uint16_t MaxClock; /* This is either DCFCLK or SOCCLK (in MHz) */ member
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| D | smu13_driver_if_yellow_carp.h | 51 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz) member
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| D | smu12_driver_if.h | 52 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz) member
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| D | smu11_driver_if_vangogh.h | 51 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz) member
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| D | smu9_driver_if.h | 329 uint16_t MaxClock; // This is either DCEFCLK or SOCCLK (in MHz) member
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| D | smu11_driver_if.h | 680 uint16_t MaxClock; member
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| D | smu11_driver_if_navi10.h | 1022 uint16_t MaxClock; // This is either DCEFCLK or SOCCLK (in MHz) member
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| D | smu11_driver_if_sienna_cichlid.h | 1479 uint16_t MaxClock; // This is either DCEFCLK or SOCCLK (in MHz) member
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
| D | dcn30_clk_mgr_smu_msg.h | 52 uint16_t MaxClock; // This is either DCEFCLK or SOCCLK (in MHz) member
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| D | dcn30_clk_mgr.c | 379 …table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MaxClock = clk_mgr->base.bw_params->wm_table.nv_entr… in dcn3_notify_wm_ranges()
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| /drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| D | smu_helper.c | 741 table->WatermarkRow[1][i].MaxClock = in smu_set_watermarks_for_clocks_ranges()
762 table->WatermarkRow[0][i].MaxClock = in smu_set_watermarks_for_clocks_ranges()
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| D | smu_helper.h | 37 uint16_t MaxClock; member
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| /drivers/gpu/drm/amd/pm/swsmu/smu13/ |
| D | yellow_carp_ppt.c | 529 table->WatermarkRow[WM_DCFCLK][i].MaxClock = in yellow_carp_set_watermarks_table()
543 table->WatermarkRow[WM_SOCCLK][i].MaxClock = in yellow_carp_set_watermarks_table()
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| /drivers/gpu/drm/amd/pm/inc/vega12/ |
| D | smu9_driver_if.h | 573 uint16_t MaxClock; member
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| /drivers/gpu/drm/amd/pm/swsmu/smu12/ |
| D | renoir_ppt.c | 1050 table->WatermarkRow[WM_DCFCLK][i].MaxClock = in renoir_set_watermarks_table()
1066 table->WatermarkRow[WM_SOCCLK][i].MaxClock = in renoir_set_watermarks_table()
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| /drivers/gpu/drm/amd/pm/swsmu/smu11/ |
| D | vangogh_ppt.c | 1578 table->WatermarkRow[WM_DCFCLK][i].MaxClock = in vangogh_set_watermarks_table()
1592 table->WatermarkRow[WM_SOCCLK][i].MaxClock = in vangogh_set_watermarks_table()
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| D | navi10_ppt.c | 1946 table->WatermarkRow[WM_DCEFCLK][i].MaxClock = in navi10_set_watermarks_table()
1960 table->WatermarkRow[WM_SOCCLK][i].MaxClock = in navi10_set_watermarks_table()
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| D | sienna_cichlid_ppt.c | 1688 table->WatermarkRow[WM_DCEFCLK][i].MaxClock = in sienna_cichlid_set_watermarks_table()
1702 table->WatermarkRow[WM_SOCCLK][i].MaxClock = in sienna_cichlid_set_watermarks_table()
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